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msd -m32170-u-0003 mitsubishi electric corporation mitsubishi electric semiconductor systems corporation note information in this manual may be changed without prior notice. mitsubishi 32-bit risc single-chip microcomputers m32r family m32r/e series 2000-03-17 ver0.10 group m32170f6vfp/wg m32170f4vfp/wg m32170f3vfp/wg users manual 32170 preliminary advanced and ever advancing
keep safety first in your circuit designs! notes regarding these materials l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). l when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semicon ductor product distributor for further details on these materials or the products con tained therein.
preface this manual describes the hardware specifica- tions of mitsubishis 32170 group of 32-bit cmos microcomputers. this manual was created to help you under- stand the hardware specifications of the 32170-group microcomputers so you can take full advantage of the versatile performance ca- pabilities of these microcomputers. the cpu features and the functionality of each internal peripheral circuit are described in detail, which we hope will prove useful for your circuit de- sign. for details about the m32r-family software products and development support tools, please refer to the users manuals and related other documentation included with your prod- ucts and tools.
how to read internal i/o register tables ? bit numbers: each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are d0-d7, and those at odd addresses are d8-d15. ? state of register at reset: represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column ? .) ? at read: ... read enabled ? ... read disabled (read value invalid) 0 ... read always as 0 1 ... read always as 1 ? at write: : write enabled : write enable conditionally (include some conditions at write) - : write disabled (written value invalid) abit 12 34 d0 d bit name function w r 0 not assigned. 0 1 abit (...................) 0: ----- 1: ----- 3 2 not implemented in the shaded portion. bbit cbit bbit (...................) cbit (...................) 0: ----- 1: ----- 0: ----- 1: ----- registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes). 1 2 3 4
(1) contents chapter 1 overview 1.1 outline of the 32170 .......................................................................................... 1-2 1.1.1 m32r family cpu core ............................................................................. 1-2 1.1.2 built-in multiply-accumulate operation function ........................................ 1-3 1.1.3 built-in flash memory and ram ................................................................. 1-3 1.1.4 built-in clock frequency multiplier ............................................................. 1-4 1.1.5 built-in powerful peripheral functions ........................................................ 1-4 1.1.6 built-in full-can function .......................................................................... 1-6 1.1.7 built-in debug function .............................................................................. 1-6 1.2 block diagram ................................................................................................... 1-7 1.3 pin function .................................................................................................... 1-10 1.4 pin layout ........................................................................................................ 1-18 chapter 2 cpu 2.1 cpu registers ................................................................................................... 2-2 2.2 general-purpose registers .............................................................................. 2-2 2.3 control registers .............................................................................................. 2-3 2.3.1 processor status word register: psw (cr0) ............................................ 2-4 2.3.2 condition bit register: cbr (cr1) ............................................................. 2-5 2.3.3 interrupt stack pointer: spi (cr2) .............................................................. 2-5 user stack pointer: spu (cr3) .................................................................. 2-5 2.3.4 backup pc: bpc (cr6) .............................................................................. 2-5 2.4 accumulator ...................................................................................................... 2-6 2.5 program counter .............................................................................................. 2-6 2.6 data formats ..................................................................................................... 2-7 2.6.1 data types ................................................................................................. 2-7 2.6.2 data formats .............................................................................................. 2-8
(2) chapter 3 address space 3.1 outline of address space ................................................................................ 3-2 3.2 operation modes ............................................................................................... 3-6 3.3 internal rom area and extended external area ............................................ 3-8 3.3.1 internal rom area ...................................................................................... 3-8 3.3.2 extended external area .............................................................................. 3-8 3.4 internal ram area and sfr area .................................................................... 3-9 3.4.1 internal ram area ...................................................................................... 3-9 3.4.2 special function register (sfr) area ........................................................ 3-9 3.5 eit vector entry .............................................................................................. 3-28 3.6 icu vector table ............................................................................................. 3-29 3.7 note about address space ............................................................................ 3-31 chapter 4 eit 4.1 outline of eit..................................................................................................... 4-2 4.2 eit event ............................................................................................................ 4-3 4.2.1 exception .................................................................................................... 4-3 4.2.2 interrupt ...................................................................................................... 4-3 4.2.3 trap ............................................................................................................ 4-3 4.3 eit processing procedure ............................................................................... 4-4 4.4 eit processing mechanism ............................................................................. 4-6 4.5 acceptance of eit event .................................................................................. 4-7 4.6 saving and restoring the pc and psw .......................................................... 4-8 4.7 eit vector entry .............................................................................................. 4-10 4.8 exception processing .................................................................................... 4-11 4.8.1 reserved instruction exception (rie) ....................................................... 4-11 4.8.2 address exception (ae) ............................................................................ 4-13 4.9 interrupt processing ....................................................................................... 4-15 4.9.1 reset interrupt (ri) ................................................................................... 4-15 4.9.2 system break interrupt (sbi) .................................................................... 4-16
(3) 4.9.3 external interrupt (ei) ............................................................................... 4-18 4.10 trap processing ............................................................................................ 4-20 4.10.1 trap (trap) ........................................................................................... 4-20 4.11 eit priority levels ......................................................................................... 4-22 4.12 example of eit processing .......................................................................... 4-23 chapter 5 interrupt controller (icu) 5.1 outline of interrupt controller (icu) ................................................................ 5-2 5.2 interrupt sources of internal peripheral i/os ................................................. 5-4 5.3 icu-related registers ...................................................................................... 5-6 5.3.1 interrupt vector register ............................................................................. 5-7 5.3.2 interrupt mask register .............................................................................. 5-8 5.3.3 sbi (system break interrupt) control register ........................................... 5-9 5.3.4 interrupt control registers ........................................................................ 5-10 5.4 icu vector table ............................................................................................. 5-14 5.5 description of interrupt operation ................................................................ 5-17 5.5.1 acceptance of internal peripheral i/o interrupts ....................................... 5-17 5.5.2 processing of internal peripheral i/o interrupts by handlers ................... 5-20 5.6 description of system break interrupt (sbi) operation .............................. 5-22 5.6.1 acceptance of sbi .................................................................................... 5-22 5.6.2 sbi processing by handler ....................................................................... 5-22 chapter 6 internal memory 6.1 outline of the internal memory ........................................................................ 6-2 6.2 internal ram ...................................................................................................... 6-2 6.3 internal flash memory ...................................................................................... 6-2 6.4 registers associated with the internal flash memory .................................. 6-3 6.4.1 flash mode register ................................................................................... 6-4 6.4.2 flash status registers ................................................................................ 6-5 6.4.3 flash controle registers ............................................................................ 6-8
(4) 6.4.4 virtual flash l bank registers ................................................................. 6-14 6.4.5 virtual flash s bank registers ................................................................. 6-15 6.5 programming of the internal flash memory ................................................. 6-16 6.5.1 outline of programming flash memory .................................................... 6-16 6.5.2 controlling operation mode during programming flash .......................... 6-22 6.5.3 programming procedure to the internal flash memory ............................ 6-25 6.5.4 flash write time (for reference) ............................................................. 6-40 6.6 boot rom ........................................................................................................ 6-42 6.7 virtual flash emulation function .................................................................. 6-43 6.7.1 virtual flash emulation area .................................................................... 6-45 6.7.2 entering virtual flash emulation mode .................................................... 6-52 6.7.3 application example of virtual flash emulation mode ............................. 6-53 6.8 connecting to a serial programmer ............................................................. 6-55 6.9 precautions to be taken when rewriting flash memory ........................... 6-57 chapter 7 reset 7.1 outline of reset ................................................................................................ 7-2 7.2 reset operation ................................................................................................ 7-2 7.2.1 reset at power-on ...................................................................................... 7-2 7.2.2 reset during operation ............................................................................... 7-2 7.2.3 reset vector relocation during flash rewrite ........................................... 7-2 7.3 internal state immediately after reset release ............................................. 7-3 7.4 things to be considered after reset release .............................................. 7-4 chapter 8 input/output ports and pin functions 8.1 outline of input/output ports .......................................................................... 8-2 8.2 selecting pin functions ................................................................................... 8-4 8.3 input/output port related registers ............................................................... 8-6 8.3.1 port data registers .................................................................................... 8-8 8.3.2 port direction registers ............................................................................ 8-10 8.3.3 port operation mode registers ................................................................ 8-12
(5) chapter 10 multijunction timers 10.1 outline of multijunction timers ................................................................... 10-2 10.2 common units of multijunction timer ........................................................ 10-9 10.2.1 timer common register map ................................................................. 10-9 10.2.2 prescaler unit ....................................................................................... 10-12 10.2.3 clock bus/input-output event bus control unit ................................... 10-13 8.4 port peripheral circuits .................................................................................. 8-31 chapter 9 dmac 9.1 outline of the dmac ......................................................................................... 9-2 9.2 dmac related registers .................................................................................. 9-4 9.2.1 dma channel control register .................................................................. 9-6 9.2.2 dma software request generation registers ......................................... 9-17 9.2.3 dma source address registers ............................................................... 9-18 9.2.4 dma destination address registers ........................................................ 9-19 9.2.5 dma transfer count registers ................................................................. 9-20 9.2.6 dma interrupt request status registers .................................................. 9-21 9.2.7 dma interrupt mask registers .................................................................. 9-23 9.3 functional description of the dmac ............................................................ 9-27 9.3.1 cause of dma request ............................................................................ 9-27 9.3.2 dma transfer processing procedure ....................................................... 9-31 9.3.3 starting dma ............................................................................................ 9-32 9.3.4 channel priority ........................................................................................ 9-32 9.3.5 gaining and releasing control of the internal bus ................................... 9-32 9.3.6 transfer units ........................................................................................... 9-33 9.3.7 transfer counts ........................................................................................ 9-33 9.3.8 address space ......................................................................................... 9-33 9.3.9 transfer operation .................................................................................... 9-33 9.3.10 end of dma and interrupt ....................................................................... 9-37 9.3.11 status of each register after completion of dma transfer ................... 9-37 9.4 precautions about the dmac ........................................................................ 9-38
(6) 10.2.4 input processing control unit ............................................................... 10-18 10.2.5 output flip-flop control unit ................................................................ 10-26 10.2.6 interrupt control unit ............................................................................ 10-37 10.3 top (output-related 16-bit timer) ............................................................. 10-63 10.3.1 outline of top ...................................................................................... 10-63 10.3.2 outline of each mode of top ............................................................... 10-65 10.3.3 top related register map ................................................................... 10-67 10.3.4 top control registers .......................................................................... 10-70 10.3.5 top counters (top0ct-top10ct) .................................................... 10-77 10.3.6 top reload registers (top0rl-top10rl) ....................................... 10-78 10.3.7 top correction registers (top0cc-top10cc) ................................ 10-79 10.3.8 top enable control register ............................................................... 10-80 10.3.9 operation in top single-shot output mode (with correction function) .. 10-84 10.3.10 operation in top delayed single-shot output mode (with correction function) 10-91 10.3.11 operation in top continuous output mode (without correction function) . 10-96 10.4 tio (input/output-related 16-bit timer) ................................................... 10-100 10.4.1 outline of tio ..................................................................................... 10-100 10.4.2 outline of each mode of tio .............................................................. 10-102 10.4.3 tio related register map .................................................................. 10-105 10.4.4 tio control registers ......................................................................... 10-108 10.4.5 tio counter (tio0ct-tio9ct) .......................................................... 10-119 10.4.6 tio reload 0/ measure register (tio0rl0-tio9rl0) ...................... 10-120 10.4.7 tio reload 1 registers (tio0rl1-tio9rl1) .................................... 10-121 10.4.8 tio enable control registers ............................................................. 10-122 10.4.9 operation in tio measure free-run/clear input modes ..................... 10-125 10.4.10 operation in tio noise processing input mode ................................ 10-129 10.4.11 operation in tio pwm output mode ................................................. 10-130 10.4.12 operation in tio single-shot output mode (without correction function) .. 10-134 10.4.13 operation in tio delayed single-shot output mode (without correction function) .. 10-136 10.4.14 operation in tio continuous output mode (without correction function) . 10-138 10.5 tms (input-related 16-bit timer) .............................................................. 10-140 10.5.1 outline of tms .................................................................................... 10-140 10.5.2 outline of tms operation ................................................................... 10-140
(7) 10.5.3 tms related register map ................................................................ 10-142 10.5.4 tms control registers ....................................................................... 10-143 10.5.5 tms counters (tms0ct, tms1ct) .................................................. 10-145 10.5.6 tms measure registers (tms0mr3-0, tms1mr3-0) ....................... 10-146 10.5.7 operation of tms measure input ....................................................... 10-147 10.6 tml (input-related 32-bit timer) .............................................................. 10-149 10.6.1 outline of tml .................................................................................... 10-149 10.6.2 outline of tml operation ................................................................... 10-150 10.6.3 tml related register map ................................................................. 10-151 10.6.4 tml control registers ........................................................................ 10-152 10.6.5 tml counters ..................................................................................... 10-154 10.6.6 tml measure registers ..................................................................... 10-156 10.6.7 operation of tml measure input ........................................................ 10-158 10.7 tid (input-related 16-bit timer) ................................................................ 10-160 10.7.1 outline of tid ...................................................................................... 10-160 10.7.2 tid related register map .................................................................. 10-162 10.7.3 tid control &prescaler enable registers .......................................... 10-163 10.7.4 tid counters (tid0ct, tid1ct, tid2ct) ......................................... 10-166 10.7.5 tid reload registers (tid0rl, tid1rl, tid2rl) ............................. 10-167 10.7.6 outline of each mode of tid .............................................................. 10-168 10.8 tod (output-related 16-bit timer) ........................................................... 10-173 10.8.1 outline of tod .................................................................................... 10-173 10.8.2 outline of each mode of tod ............................................................. 10-175 10.8.3 tod related register map ................................................................ 10-177 10.8.4 tod control registers (tod0cr) ..................................................... 10-180 10.8.5 tod counters ..................................................................................... 10-182 10.8.6 tod reload 0 registers ..................................................................... 10-184 10.8.7 tod reload 1 registers ..................................................................... 10-186 10.8.8 tod enable protect registers ........................................................... 10-188 10.8.9 tod cout enable registers ............................................................... 10-190 10.8.10 operation in tod pwm output mode .............................................. 10-193 10.8.11 operation in tod single-shot output mode (without correction function) 10-197 10.8.12 operation in tod delayed single-shot output mode (without correction function) 10-199
(8) chapter 11 a-d converters 11.1 outline of a-d converter .............................................................................. 11-2 11.1.1 conversion modes .................................................................................. 11-6 11.1.2 operation modes .................................................................................... 11-7 11.1.3 special operation modes ..................................................................... 11-11 11.1.4 a-d converter interrupt and dma transfer requests .......................... 11-14 11.2 a-d converter related registers .............................................................. 11-15 11.2.1 a-d single mode register 0 ................................................................. 11-19 11.2.2 a-d single mode register 1 ................................................................. 11-23 11.2.3 a-d scan mode register 0 ................................................................... 11-26 11.2.4 a-d scan mode register 1 ................................................................... 11-30 11.2.5 a-d successive approximation register .............................................. 11-33 11.2.6 a-d0 comparate data register ............................................................. 11-35 11.2.7 10-bit a-d data registers ..................................................................... 11-37 11.2.8 8-bit a-d data registers ....................................................................... 11-39 10.8.13 operation in tod continuous output mode (without correction function) . 10-201 10.9 tom (output-related 16-bit timer) .......................................................... 10-203 10.9.1 outline of tom ................................................................................... 10-203 10.9.2 outline of each mode of tom ............................................................ 10-205 10.9.3 tom related register map ................................................................ 10-207 10.9.4 tom control registers ....................................................................... 10-209 10.9.5 tom counters .................................................................................... 10-210 10.9.6 tom reload 0 registers .................................................................... 10-211 10.9.7 tom reload 1 registers .................................................................... 10-212 10.9.8 tom enable protect registers ........................................................... 10-213 10.9.9 tom count enable registers ............................................................. 10-214 10.9.10 operation in tom pwm output mode ............................................... 10-216 10.9.11 operation in tom single-shot output mode (without correction function) 10-220 10.9.12 operation in tom single-shot pwm output mode (without correction function) .... 10-222 10.9.13 operation in tom continuous output mode (without correction function) ... 10-224 10.9.14 example application for using the 32170 in motor control ............... 10-226
(9) 11.3 functional description of a-d converters ............................................... 11-41 11.3.1 how to find along input voltages ........................................................ 11-41 11.3.2 a-d conversion by successive approximation method ....................... 11-42 11.3.3 comparator operation .......................................................................... 11-44 11.3.4 calculation of the a-d conversion time ............................................... 11-45 11.3.5 definition of the a-d conversion accuracy ........................................... 11-48 11.4 precautions on using a-d converters ...................................................... 11-51 chapter 12 serial i/o 12.1 outline of serial i/o ....................................................................................... 12-2 12.2 serial i/o related registers ......................................................................... 12-6 12.2.1 sio interrupt related registers .............................................................. 12-7 12.2.2 sio interrupt control registers .............................................................. 12-9 12.2.3 sio transmit control registers ............................................................ 12-16 12.2.4 sio transmit/receive mode registers ................................................ 12-18 12.2.5 sio transmit buffer registers .............................................................. 12-21 12.2.6 sio receive buffer registers ............................................................... 12-22 12.2.7 sio receive control registers ............................................................. 12-23 12.2.8 sio baud rate registers ..................................................................... 12-26 12.3 transmit operation in csio mode ............................................................ 12-28 12.3.1 setting the csio baud rate ................................................................. 12-28 12.3.2 initial settings for csio transmission .................................................. 12-29 12.3.3 starting csio transmission ................................................................. 12-31 12.3.4 successive csio transmission ........................................................... 12-31 12.3.5 processing at end of csio transmission ............................................ 12-32 12.3.6 transmit interrupt ................................................................................. 12-32 12.3.7 transmit dma transfer request .......................................................... 12-32 12.3.8 typical csio transmit operation ......................................................... 12-34 12.4 receive operation in csio mode .............................................................. 12-36 12.4.1 initial settings for csio reception ....................................................... 12-36 12.4.2 starting csio reception ...................................................................... 12-38 12.4.3 processing at end of csio reception .................................................. 12-38
(10) 12.4.4 about successive reception ................................................................ 12-39 12.4.5 flags indicating the status of csio receive operation ....................... 12-40 12.4.6 typical csio receive operation .......................................................... 12-41 12.5 precautions on using csio mode ............................................................. 12-43 12.6 transmit operation in uart mode ........................................................... 12-45 12.6.1 setting the uart baud rate ................................................................ 12-45 12.6.2 uart transmit/receive data formats ................................................ 12-46 12.6.3 initial settings for uart transmission ................................................. 12-48 12.6.4 starting uart transmission ................................................................ 12-50 12.6.5 successive uart transmission .......................................................... 12-50 12.6.6 processing at end of uart transmission ........................................... 12-51 12.6.7 transmit interrupt ................................................................................. 12-51 12.6.8 transmit dma transfer request .......................................................... 12-51 12.6.9 typical uart transmit operation ........................................................ 12-53 12.7 receive operation in uart mode ............................................................. 12-55 12.7.1 initial settings for uart reception ...................................................... 12-55 12.7.2 starting uart reception ..................................................................... 12-57 12.7.3 processing at end of uart reception ................................................. 12-57 12.7.4 typical uart receive operation ......................................................... 12-59 12.8 fixed period clock output function ......................................................... 12-61 12.9 precautions on using uart mode ............................................................ 12-62 chapter 13 can module 13.1 outline of the can module .......................................................................... 13-2 13.2 can module related registers ................................................................... 13-4 13.2.1 can control register ............................................................................. 13-8 13.2.2 can status register ............................................................................. 13-11 13.2.3 can extended id register ................................................................... 13-15 13.2.4 can configuration register ................................................................. 13-16 13.2.5 can time stamp count register ......................................................... 13-19 13.2.6 can error count registers .................................................................. 13-20 13.2.7 can baud rate prescaler .................................................................... 13-21
(11) 13.2.8 can interrupt related registers .......................................................... 13-22 13.2.9 can mask registers ............................................................................ 13-30 13.2.10 can message slot control registers ................................................. 13-34 13.2.11 can message slots ............................................................................ 13-38 13.3 can protocol ............................................................................................... 13-53 13.3.1 can protocol frame ............................................................................. 13-53 13.4 initializing the can module ........................................................................ 13-56 13.4.1 initialization of the can module ............................................................ 13-56 13.5 transmitting data frames .......................................................................... 13-59 13.5.1 data frame transmit procedure .......................................................... 13-59 13.5.2 data frame transmit operation ........................................................... 13-61 13.5.3 transmit abort function ....................................................................... 13-62 13.6 receiving data frames .............................................................................. 13-63 13.6.1 data frame receive procedure ........................................................... 13-63 13.6.2 data frame receive operation ............................................................ 13-65 13.6.3 reading out received data frames .................................................... 13-67 13.7 transmitting remote frames .................................................................... 13-69 13.7.1 remote frame transmit procedure ..................................................... 13-69 13.7.2 remote frame transmit operation ...................................................... 13-71 13.7.3 reading out received data frames when set for remote frame transmission .. 13-74 13.8 receiving remote frames ......................................................................... 13-76 13.8.1 remote frame receive procedure ...................................................... 13-76 13.8.2 remote frame receive operation ....................................................... 13-78 chapter 14 real-time debugger (rtd) 14.1 outline of the real-time debugger (rtd) .................................................. 14-2 14.2 pin function of the rtd ............................................................................... 14-3 14.3 functional description of the rtd .............................................................. 14-4 14.3.1 outline of rtd operation ....................................................................... 14-4 14.3.2 operation of rdr (real-time ram content output) .............................. 14-5 14.3.3 operation of wrr (ram content forcible rewrite) .............................. 14-7 14.3.4 operation of ver (continuous monitor) ................................................. 14-9
(12) 14.3.5 operation of vei (interrupt request) .................................................... 14-10 14.3.6 operation of rcv (recover from runaway) ........................................ 14-11 14.3.7 method to set a specified address when using the rtd .................... 14-12 14.3.8 resetting the rtd ................................................................................ 14-13 14.4 typical connection with the host ............................................................. 14-14 chapter 15 external bus interface 15.1 external bus interface related signals ...................................................... 15-2 15.2 read/write operations ................................................................................. 15-6 15.3 bus arbitration ............................................................................................ 15-12 15.4 typical connection of external extension memory ................................ 15-14 chapter 16 wait controller 16.1 outline of the wait controller ...................................................................... 16-2 16.2 wait controller related registers ............................................................... 16-4 16.2.1 wait cycles control register .................................................................. 16-5 16.3 typical operation of the wait controller .................................................... 16-6 chapter 17 ram backup mode 17.1 outline ............................................................................................................ 17-2 17.2 example of ram backup when power is down ......................................... 17-2 17.2.1 normal operating state .......................................................................... 17-3 17.2.2 ram backup state ................................................................................. 17-4 17.3 example of ram backup for saving power consumption ....................... 17-5 17.3.1 normal operating state .......................................................................... 17-6 17.3.2 ram backup state ................................................................................. 17-7 17.3.3 precautions to be observed at power-on .............................................. 17-8 17.4 exiting ram backup mode (wakeup) ......................................................... 17-9
(13) chapter 18 oscillation circuit 18.1 oscillator circuit ........................................................................................... 18-2 18.1.1 example of an oscillator circuit .............................................................. 18-2 18.1.2 system clock output function ............................................................... 18-3 18.1.3 oscillation stabilization time at power-on ............................................. 18-4 18.2 clock generator circuit ................................................................................ 18-5 chapter 19 jtag 19.1 outline of jtag ............................................................................................. 19-2 19.2 configuration of the jtag circuit ............................................................... 19-3 19.3 jtag registers ............................................................................................. 19-4 19.3.1 instruction register (jtagir) ................................................................. 19-4 19.3.2 data registers ........................................................................................ 19-5 19.4 basic operation of jtag ............................................................................. 19-6 19.4.1 outline of jtag operation ..................................................................... 19-6 19.4.2 ir path sequence ................................................................................... 19-8 19.4.3 dr path sequence ............................................................................... 19-10 19.4.4 examining and setting data registers ................................................. 19-12 19.5 boundary scan description language ..................................................... 19-14 19.6 precautions about board design when connecting jtag ..................... 19-34 chapter 20 power-up/power-shutdown sequence 20.1 configuration of the power supply circuit ................................................ 20-2 20.2 power-on sequence ..................................................................................... 20-3 20.2.1 power-on sequence when not using ram backup ............................. 20-3 20.2.2 power-on sequence when using ram backup .................................... 20-4 20.3 power-shutdown sequence ......................................................................... 20-5 20.3.1 power-shutdown sequence when not using ram backup .................. 20-5 20.3.2 power-shutdown sequence when using ram backup ......................... 20-6
(14) chapter 21 electrical characteristics 21.1 absolute maximum ratings ......................................................................... 21-2 21.2 recommended operating conditions ........................................................ 21-3 21.3 dc characteristics ........................................................................................ 21-5 21.3.1 electrical characteristics ........................................................................ 21-5 21.3.2 flash related electrical characteristics ............................................... 21-10 21.4 a-d conversion characteristics ................................................................ 21-11 21.5 ac characteristics ...................................................................................... 21-12 21.5.1 timing requirements ............................................................................ 21-12 21.5.2 switching characteristics ...................................................................... 21-15 21.5.3 ac characteristics ................................................................................ 21-18 chapter 22 typical characteristics 22.1 a-d conversion characteristics .................................................................. 22-2 appendix 1 mechanical specifications appendix 1.1 dimensional outline drawing ....................................... appendix 1-2 appendix 2 instruction processing time appendix 2.1 32170 instruction processing time ............................. appendix 2-2 appendix 3 precautions about noise appendix 3.1 precautions about noise .............................................. appendix 3-2 appendix 3.1.1 reduction of wiring length ........................................ appendix 3-2 appendix 3.1.2 inserting a bypass capacitor between vss and vcc lines ...... appendix 3-4 appendix 3.1.3 processing analog input pin wiring ........................... appendix 3-5 appendix 3.1.4 consideration about the oscillator .............................. appendix 3-6 appendix 3.1.5 processing input/output ports .................................... appendix 3-8
chapter 1 chapter 1 overview 1.1 outline of the 32170 1.2 block diagram 1.3 pin function 1.4 pin layout
1 1-2 ver.0.10 1.1 outline of the 32170 1.1.1 m32r family cpu core (1) based on risc architecture ? the 32170 is a 32-bit risc single-chip microcomputer which is built around the m32r family cpu core (hereafter referred to as the m32r) and incorporates flash memory, ram, and various other peripheral functions-all integrated into a single chip. ? the m32r is based on risc architecture. memory access is performed using load and store instructions, and various arithmetic operations are executed using register-to-register operation instructions. the m32r internally contains sixteen 32-bit general-purpose registers and has 83 distinct instructions. ? the m32r supports compound instructions such as load & address update and store & address update, in addition to ordinary load and store instructions. these compound instructions help to speed up data transfers. (2) 5-stage pipelined processing ? the m32r uses 5-stage pipelined instruction processing consisting of instruction fetch, decode, execute, memory access, and write back. not just load and store instructions or register-to-register operation instructions, compound instructions such as load & address update and store & address update also are executed in one cycle. ? instructions are entered into the execution stage in the order they are fetched, but this does not always mean that the first instruction entered is executed first. if the execution of a load or store instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a register-to-register operation instruction entered later may be executed before said load or store instruction. by using "out-of-order-completion" like this, the m32r controls instruction execution without wasting clock cycles. (3) compact instruction code ? the m32r instructions come in two types: one consisting of 16 bits in length, and the other consisting of 32 bits in length. use of the 16-bit length instruction format especially helps to suppress the program code size. ? some 32-bit long instructions can branch directly to a location 32 mbytes forward or backward from the instruction address being executed. compared to architectures where address space is segmented, this direct jump allows for easy programming. overview 1.1 outline of the 32170
1 1-3 ver.0.10 overview 1.1 outline of the 32170 1.1.2 built-in multiply-accumulate operation function (1) built-in high-speed multiplier ? the m32r incorporates a 32-bit 16-bit high-speed multiplier which enables it to execute a 32-bit 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 mhz internal cpu clock). (2) supports multiply-accumulate operation instructions comparable to dsp ? the m32r supports the following four modes of multiply-accumulate operation instructions (or multiplication instructions) using a 56-bit accumulator. any of these operations can be executed in one cycle. ? 16 high-order register bits 16 high-order register bits 16 low-order register bits 16 low-order register bits a entire 32 register bits 16 high-order register bits ? entire 32 register bits 16 low-order register bits the m32r has instructions to round off the value stored in the accumulator to 16 or 32 bits, as well as instructions to shift the accumulator value to adjust digits and store the digit-adjusted value in a register. these instructions also can be executed in one cycle, so that when combined with high-speed data transfer instructions such as load & address update and store & address update, they enable the m32r to exhibit high data processing capability comparable to that of dsp. 1.1.3 built-in flash memory and ram ? the 32170 contains flash memory and ram which can be accessed with no wait states, allowing you to build a high-speed embedded system. ? the internal flash memory allows for on-board programming (you can write to it while being mounted on the printed circuit board). use of flash memory means the chip engineered at the development phase can be used directly in mass-production, so that you can smoothly migrate from prototype to mass-production without changing the printed circuit board. ? the internal flash memory can be rewritten 100 times. ? the internal flash memory has a pseudo-flash emulation function, allowing the internal ram to be artificially mapped into part of the internal flash memory. this function, when combined with the internal real-time debugger (rtd), facilitates data tuning on rom tables. ? the internal ram can be accessed for read or rewrite from an external device independently of the m32r by using rtd (real-time debugger). it is communicated with external devices by rtd's exclusive clock-synchronized serial i/o.
1 1-4 ver.0.10 overview 1.1 outline of the 32170 1.1.4 built-in clock frequency multiplier ? the 32170 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2. if the input clock frequency is 10.0 mhz, the cpu clock frequency will be 40 mhz and the internal clock frequency 20 mhz. 1.1.5 built-in powerful peripheral functions (1) built-in multijunction timer (mjt) ? the multijunction timer is configured with the following timers: ? 16-bit output-related timer 35 channels 16-bit input/output-related timer 10 channels a 16-bit input-related timer 11 channels (incorporating three channels of multiply-by-4 counter) ? 32-bit input-related timer 8 channels each timer has multiple modes of operation, which can be selected according of the purpose of use. the multijunction timer has internal clock bus, input event bus, and output event bus, allowing multiple timers to be combined for use internally. this provides a flexible way to make use of timer functions. the output-related timers (top) have a correction function. this function allows the timer's count value in progress to be increased or reduced as desired, thus materializing real-time output control. (2) built-in 10-channel dma ? the 10-channel dma is built-in, supporting data transfers between internal peripheral i/os or between internal peripheral i/o and internal ram. not only can dma transfer requests be generated in software, but can also be triggered by a signal generated by an internal peripheral i/o (e.g., a-d converter, mjt, or serial i/o). ? cascaded connection between dma channels (dma transfer in a channel is started by completion of transfer in another) is also supported, allowing for high-speed transfer processing without imposing any extra load on the cpu. (3) built-in 16-channel a-d converters ? the 32170 contains two 16-channel a-d converters which can convert data in 10-bit resolution. in addition to single a-d conversion in each channel, successive a-d conversion in four, eight, or 16 channels combined into one unit is possible. ? in addition to ordinary a-d conversion, a comparator mode is supported in which the a-d conversion result is compared with a given set value to determine the relative magnitudes of two quantities. ? when a-d conversion is completed, the 32170 can generate not only an interrupt, but can also generate a dma transfer request. ? the 32170 supports two read out modes, so that a-d conversion results can be read out in 8 bits or 10 bits.
1 1-5 ver.0.10 overview 1.1 outline of the 32170 (4) high-speed serial i/o ? the 32170 incorporates 6 channels of serial i/o, which can be set for clock-synchronized serial i/o or uart. ? when set for clock-synchronized serial i/o, the data transfer rate is a high 2 mbits per second. ? when data reception is completed or the transmit buffer becomes empty, the serial i/o can generate a dma transfer request signal. (5) built-in real-time debugger (rtd) ? the real-time debugger (rtd) provides a function for the m32r/e's internal ram to be accessed directly from an external device. the debugger communicates with external devices through its exclusive clock-synchronized serial i/o. ? by using the rtd, you can read the contents of the internal ram or rewrite its data from an external device independently of the m32r. ? the debugger can generate an rtd interrupt to notify that rtd-based data transmission or reception is completed. (6) eight-level interrupt controller ? the interrupt controller manages interrupt requests from each internal peripheral i/o by resolving interrupt priority in eight levels including an interrupt-disabled state. also, it can accept external interrupt requests due to power-down detection or generated by a watchdog timer as a system break interrupt (sbi). (7) three operation modes ? the m32r/e has three operation modes-single-chip mode, extended external mode, and processor mode. the address space and external pin functions of the m32r/e are switched over according to a mode in which it operates. the mod0 and mod1 pins are used to set a mode. (8) wait controller ? the wait controller supports access to external devices by the m32r. in all but single-chip mode, the extended external area provides 4 mbytes of space.
1 1-6 ver.0.10 1.1.6 built-in full-can function ? the 32170 contains can specification v2.0b-compliant can module, thereby providing 16 message slots. 1.1.7 built-in debug function ? the 32170 supports jtag interface. boundary scan test can be performed using this jtag interface. overview 1.1 outline of the 32170
1 1-7 ver.0.10 overview 1.2 block diagram 1.2 block diagram figure 1.2.1 shows a block diagram of the 32170. features of each block are shown in tables 1.2.1 through 1.2.3. figure 1.2.1 block diagram of the 32170 pll clock generator circuit internal bus interface address data internal ram (m32170f6:40kb) (m32170f4:32kb) (m32170f3:32kb) internal flash memory (m32170f6:768kb) (m32170f4:512kb) (m32170f3:384kb) m32r cpu core (max 40mhz) multiplier- accumulator (32 x 16 + 56) dmac (10 channels) multijunction timer (mjt: 64 channels) serial i/o (6 channels) a-d converter (10-bit resolution, 16 channels) x 2 wait controller interrupt controller (31 sources, 8 levels) real-time debugger (rtd) external bus interface internal 16-bit bus internal 32-bit bus input/output port (jtag), 157 lines full can (1 channel) 32170
1 1-8 ver.0.10 overview 1.2 block diagram table 1.2.1 features of the m32r family cpu core functional block features m32r family ? bus specifications cpu core basic bus cycle: 25 ns (when operating with 40 mhz cpu clock) logical address space: 4gbytes, linear extended external area: maximum 4 mbytes external data bus: 16 bits ? implementation: five-stage pipeline ? internal 32-bit architecture for the core ? register configuration general-purpose register: 32 bits 16 registers control register: 32 bits 5 registers instruction set 16-bit and 32-bit instruction formats 83 distinct instructions and 9 addressing modes built-in multiplier/accumulator (32 16 + 56) table 1.2.2 features of internal memory functional block features ram ? capacity m32170f6 : 40 kbytes m32170f4, m32170f3 : 32 kbytes ? no-wait access (when operating with 40 mhz cpu clock) ? by using rtd (real-time debugger), the internal ram can be accessed for read or rewrite from external devices independently of the m32r. flash memory ? capacity m32170f6 : 768 kbytes m32170f4 : 512 kbytes m32170f3 : 384 kbytes ? no-wait access (when operating with 40 mhz cpu clock) ? durability: can be rewritten 100 times
1 1-9 ver.0.10 table 1.2.3 features of internal peripheral i/o functional block features dma ? 10-channel dma ? supports transfer between internal peripheral i/os and between internal peripheral i/o and internal ram. ? capable of advanced dma transfer when operating in combination with internal peripheral i/o ? capable of cascaded connection between dma channels (dma transfer in a channel is started by completion of transfer in another) multijunction ? 64-channel multifunction timer ? contains output-related timer 35 channels, input/output-related timer 10 channels, 16-bit input-related timer 11 channels, and 32-bit input-related timer 8 channels. capable of flexible timer configuration by mutual connection between each channel. a-d converter 16-channel, 10-bit resolution a-d converter 2 units incorporates comparator mode can generate interrupt or start dma transfer upon completion of a-d conversion. can read out conversion results in 8 or 10 bits. serial i/o 6-channel serial i/o can be set for clock-synchronized serial i/o or uart. capable of high-speed data transfer at 2 mbits per second when clock synchronized or 156 kbits per second during uart. real-time debugger can rewrite or monitor the internal ram independently of the cpu by command input from an external source. has its exclusive clock-synchronized serial port. interrupt controller accepts and manages interrupt requests from internal peripheral i/o. resolves interrupt priority in 8 levels including interrupt-disabled state. wait controller controls wait state for access to extended external areas. can insert 1 to 4 wait cycles by setting in software and extend wait period by external wait signal. clock pll multiply-by-4 clock generator circuit maximum 40 mhz of cpu clock (cpu, internal rom, internal ram access) maximum 20 mhz of internal peripheral clock (peripheral module access) maximum external input clock frequency=10 mhz can sixteen message slots jtag capable of boundary scan overview 1.2 block diagram
1 1-10 ver.0.10 overview 1.3 pin function 1.3 pin function figure 1.3.1 shows a pin function diagram of the 32170 in 240qfp package. figure 1.3.2 shows a pin function diagram of the 32170 in 255fbga package. table 1.3.1 explains the function of each pin of the 32170. table 1.3.2 explains the function of the dedicated debug pins of the 32170 in 255fbga package. figure 1.3.1 pin function diagram of 240qfp xin reset m32170f6vfp , m32170f4vfp , m32170f3vfp clock reset vcci vss 6 16 p20 ? p27/a23 ? a30 p30 ? p37/a15 ? a22 p46, p47/a13, a14 address bus 20 p00 ? p07/db0 ? db7 p10 ? p17/db8 ? db15 data bus 16 p72/hreq p73/hack bus control p71/wait interrupt controller p43/rd p44/cs0 p45/cs1 p41/blw/ble p42/bhw/bhe port 22 port 2 port 3 port 4 port 0 port 1 port 7 port 4 xout vcnt osc-vcc osc-vss mod0 mod1 mode p190 ? p197/tin26 ? tin33 p172, p173/tin24, tin25 p150 ? p157/tin0 ? tin7 p140 ? p147/tin8 ? tin15 p130 ? p137/tin16 ? tin23 34 port 19 port 17 port 15 port 14 port 13 p124 ? p127/ tclk0 ? tclk 3 4 multi- junction timer 45 p210 - p217/to37 - to44 p180 - p187/to29 - to36 p160 - p167/to21 - to28 p110 - p117/to0 - to7 p100 - p107/to8 - to15 p93 - p97/to16 - to20 port 12 port 21 port 18 port 16 port 11 port 10 port 9 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk real-time debugger port 7 p70/bclk/wr port 7 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 serial i/o port 8 16 ad1in0 ? ad1in15 a-d converter p67/adtrg avcc0, avcc1 avss0, avss1 port 6 p61-p63 port 6 avref0, avref1 vdd fvcc fp vcce 7 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 port 17 3.3v 5v 3.3v 5v 3.3v 3.3v 5v note1. : denotes blocks operating with a 3.3 v power supply. : denotes blocks operating with a 5 v power supply. 16 ad0in0 ? ad0in15 2 2 2 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 port 20 p220/ctx p221/crx can jtms jtck jtrst jtdo jtag jtdi port 22 p222, p223 port 22 p224/a11(note2) p225/a12(note2) note2. use caution when using this port because it has a debug event function. p65/sclki4/sclko4 p64/sbi port 6 p66/sclki5/sclko5 port 6 3
1 1-11 ver.0.10 overview 1.3 pin function figure 1.3.2 pin function diagram of 255fbga xin reset m32170f6vwg , M32170F4VWG , m32170f3 vwg clock reset vcci vss 6 16 p20 p27/a23 a30 p30 p37/a15 a22 p46, p47/a13, a14 address bus 20 p00 p07/db0 db7 p10 p17/db8 db15 data bus 16 p72/hreq p73/hack bus control p71/wait interrupt controller p43/rd p44/cs0 p45/cs1 p41/blw/ble p42/bhw/bhe port 22 port 2 port 3 port 4 port 0 port 1 port 7 port 4 xout vcnt osc-vcc osc-vss mod0 mod1 mode p190 p197/tin26 tin33 p172, p173/tin24, tin25 p150 p157/tin0 tin7 p140 p147/tin8 tin15 p130 p137/tin16 tin23 34 port 19 port 17 port 15 port 14 port 13 p124 p127/ tclk0 tclk 3 4 multi- junction timer 45 p210 p217/to37 to44 p180 p187/to29 to36 p160 p167/to21 to28 p110 p117/to0 to7 p100 p107/to8 to15 p93 p97/to16 to20 port 12 port 21 port 18 port 16 port 11 port 10 port 9 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk real-time debugger port 7 p70/bclk/wr port 7 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 serial i/o port 8 16 ad1in0 ad1in15 a-d converter p67/adtrg avcc0, avcc1 avss0, avss1 port 6 p61 p63 port 6 avref0, avref1 vdd fvcc fp vcce 7 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 port17 3.3v 5v 3.3v 5v 3.3v 3.3v 5v note1. : denotes blocks operating with a 3.3 v power supply : denotes blocks operating with a 5 v power supply. 16 ad0in0 ad0in15 2 2 2 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 port 20 p220/ctx p221/crx can jtms jtck jtrst jtdo jtag jtdi port 22 p222, p223 port 22 p224/a11 (note2) p225/a12 (note2) note2. use caution when using this port because it has a debug event function. p65/sclki4/sclko4 p64/sbi port 6 p66/sclki5/sclko5 port 6 3 8 trclk trsync trdata jdbi jevento jevent1 dbgug note3. 255fbga is currently under development.
1 1-12 ver.0.10 table 1.3.1 description of the 32170 pin function (1/6) type pin name signal name input/output function power vcce power supply power supply to external i/o ports (5 v). supply vcci power supply power supply to internal logic (3.3 v). vdd ram power supply power supply for internal ram backup (3.3 v). fvcc flash power supply power supply for internal flash memory (3.3 v). vss ground connect all vss to ground (gnd). clock xin, clock input clock input/output pins. these pins contains a pll-based xout output frequency multiplier circuit. apply a clock whose frequency is 1/4 the operating frequency. (when using 40 mhz cpu clock, xin input = 10.0 mhz) bclk/wr system clock output this pin outputs a clock whose frequency is twice that of external input clock. (when using 10 mhz external input clock, bclk output = 20 mhz). use this output when external operation needs to be synchronized. osc-vcc power supply power supply for pll circuit. connect osc-vcc to the power supply rail. osc-vss ground connect osc-vss to ground. vcnt pll control input this pin controls the pll circuit. connect a resistor and capacitor to it. (for external circuits, refer to section 18.1.1, "example of an oscillator circuit.") reset reset reset input this pin resets the internal circuit. mode mod0 mode input these pins set operation mode. mod1 mod0 mod1 mode 0 0 single-chip mode 0 1 extended external mode 1 0 processor mode 0 0 (boot mode) (note) 1 1 (reserved) address a11 C a30 address output the device has 20 address lines (a11-a30) to allow two bus bus channels of up to 2 mb of memory space to be added external to the chip. a31 is not output. note: for boot mode, refer to chapter 6, "internal memory." overview 1.3 pin function
1 1-13 ver.0.10 table 1.3.1 description of the 32170 pin function (2/6) type pin name signal name input/output function data db0-db15 data bus input/output these pins comprise 16-bit data bus to connect external devices. in write bus cycles, the valid byte positions to be written on the 16-bit data bus are output as bhw/bhe and blw/ble. in read cycles, data is always read from the 16-bit data bus. however, when transferring to the internal circuit of the m32r, only data at the valid byte positions are transferred. bus ___ cs0, chip select output these pins comprise external device chip select signal. for control ___ cs1 areas for which a chip select signal is output, refer to chapter 3, "address space." __ rd read output this signal is output when reading an external device. ___ ___ bhw/bhe byte high output indicates the byte position to which valid data is transferred write/enable ___ ___ when writing to an external device. bhw/bhe corresponds ___ ___ blw/ble byte low output ___ ___ to the upper address (d0-d7 is valid); blw/ble write/enable corresponds to the lower address (d8-d15 is valid). ____ wait wait input when the m32r accesses an external device, a low on this ____ wait input extends the wait cycle. ____ hreq hold request input this pin is used by an external device to request control of ____ the external bus. a low on this hreq input causes the m32r to enter a hold state. ____ hack hold output this signal is used to notify that the m32r has entered a acknowledge hold state and relinquished control of the external bus. tin 0Ctin 33 timer input input input pins for multijunction timer. to 0C to 44 timer output output output pins for the multijunction timer. tclk 0C tclk 3 timer clock input clock input pins for the multijunction timer. a-d avcc0, analog power supply avcc0 is the power supply for the a-d0 converter. avcc1 converter avcc1 is the power supply for the a-d1 converter. connect avcc0 and 1 to the power supply rail. avss0, analog ground avss0 is analog ground for the a-d0 converter. avss1 is avss1 analog ground for the a-d1 converter. connect avss0 and 1 to the ground. ad0in0 analog input input 16-channel analog input pins for the a-d0 converter. C ad0in15 ad1in0 16-channel analog input pins for the a-d1 converter. C ad1in15 overview 1.3 pin function multi- junction timer
1 1-14 ver.0.10 table 1.3.1 description of the 32170 pin function (3/6) type pin name signal name input/output function a-d vref0, reference input vref0 is the reference voltage input pin for the a-d0 converter. converter vref1 voltage input vref1 is the reference voltage input pin for the a-d1 converter. _____ adtrg conversion input hardware trigger input pin to start a-d conversion. trigger interrupt ___ sbi system break input system break interrupt (sbi) input pin for the interrupt controller interrupt controller serial i/o sclki0 / uart transmit/ input/output when channel 0 is in uart mode: sclko0 receive clock this pin outputs a clock derived from brg output by halving it . output or csio transmit/receive when channel 0 is in csio mode: clock input/output this pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. sclki1 / uart transmit/ input/output when channel 1 is in uart mode: sclko1 receive clock this pin outputs a clock derived from brg output by halving it . output or csio transmit/receive when channel 1 is in csio mode: clock input/output this pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. sclki4 / uart transmit/ input/output when channel 4 is in uart mode: sclko4 receive clock this pin outputs a clock derived from brg output by halving it . output or csio transmit/receive when channel 4 is in csio mode: clock input/output this pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. sclki5 / uart transmit/ input/output when channel 5 is in uart mode: sclko5 receive clock this pin outputs a clock derived from brg output by halving it . output or csio transmit/receive when channel 5 is in csio mode: clock input/output this pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. txd0 transmit data output transmit data output pin for serial i/o channel 0 rxd0 receive data input receive data input pin for serial i/o channel 0 overview 1.3 pin function
1 1-15 ver.0.10 real-time debugger txd1 transmit data output transmit data output pin for serial i/o channel 1. rxd1 receive data input receive data input pin for serial i/o channel 1. txd2 transmit data output transmit data output pin for serial i/o channel 2. rxd2 receive data input receive data input pin for serial i/o channel 2. txd3 transmit data output transmit data output pin for serial i/o channel 3. rxd3 receive data input receive data input pin for serial i/o channel 3. txd4 transmit data output transmit data output pin for serial i/o channel 4. rxd4 receive data input receive data input pin for serial i/o channel 4. txd5 transmit data output transmit data output pin for serial i/o channel 5. rxd5 receive data input receive data input pin for serial i/o channel 5. rtdtxd transmit data output serial data output pin for the real-time debugger. rtdrxd receive data input serial data input pin for the real-time debugger. rtdclk clock input input serial data transmit/receive clock input pin for the real-time debugger. rtdack acknowledge output this pin outputs a low pulse synchronously with the beginning clock of the real-time debugger's serial data output word. the duration of this low pulse indicates the type of command/data that the real-time debugger has received. flash fp flash protect input this mode pin has a function to protect the flash -only memory against e/w in hardware. can ctx data output output this pin outputs data from the can module. crx data input input this pin is used to input data to the can module. jtag jtms test mode input test mode select input to control state transition of the test circuit. jtck clock input clock input for the debug module and test circuit. jtrst test reset input test reset input to initialize the test circuit asynchronously. jtdi serial input input this pin is used to input test instruction code or test data serially. jtdo serial output output this pin outputs test instruction code or test data serially. overview 1.3 pin function table 1.3.1 description of the 32170 pin function (4/6) type pin name signal name input/output function
1 1-16 ver.0.10 overview 1.3 pin function table 1.3.1 description of the 32170 pin function (5/6) type pin name signal name input/output function p00 C p07 input/output input/output programmable input/output port. port 0 p10 C p17 input/output input/output programmable input/output port. port 1 p20 C p27 input/output input/output programmable input/output port. port 2 p30 C p37 input/output input/output programmable input/output port. port 3 p41 C p47 input/output input/output programmable input/output port. port 4 p61 C p67 input/output input/output programmable input/output port. port 6 (however, p64 is an input-only port.) p70 C p77 input/output input/output programmable input/output port. port 7 p82 C p87 input/output input/output programmable input/output port. port 8 p93 C p97 input/output input/output programmable input/output port. port 9 p100 input/output input/output programmable input/output port. C p107 port 10 p110 input/output input/output programmable input/output port. C p117 port 11 p124 input/output input/output programmable input/output port. C p127 port 12 p130 input/output input/output programmable input/output port. C p137 port 13 p140 input/output input/output programmable input/output port. C p147 port 14 p150 input/output input/output programmable input/output port. C p157 port 15 p160 input/output input/output programmable input/output port. C p167 port 16 input/ output port (note) note: input/output port 5 is reserved for future use.
1 1-17 ver.0.10 p172 input/output input/output programmable input/output port. C p177 port 17 p180 input/output input/output programmable input/output port. C p187 port 18 p190 input/output input/output programmable input/output port. C p197 port 19 p200 input/output input/output programmable input/output port. C p203 port 20 p210 input/output input/output programmable input/output port. C p217 port 21 p220 input/output input/output programmable input/output port. (note) C p225 port 22 (however, p221 is an input only port.) note: use caution when using p224 and p225 because they have a debug event function. table 1.3.2 description of the debug-only pin function of 255fbga type pin name signal name input/output function debog jdbi debug interrupt input debug interrupt request input pin. a low on this input request requests a debug interrupt. jevent0, event output output output synchronously with trclk. when an event occurs, jevent1 this output is driven high for a 1 trclk period. trclk trace clock output clock output pin for trace operation. trace data is output output synchronously with this clock. trsync trace packet output this is a trace packet output start signal. when the device output start signal starts outputting a trace packet, this signal is driven high for a 1 trclk period. trdata0 trace packet output trace packet output pin. - trdata7 output note: 255fbga is currently under development. table 1.3.1 description of the 32170 pin function (6/6) type pin name signal name input/output function input/ output port overview 1.3 pin function
1 1-18 ver.0.10 overview 1.4 pin layout 1.4 pin layout figure 1.4.1 shows a pin layout diagram of the 32170 in 240qfp package. figure 1.4.2 shows a pin layout diagram of the 32170 in 255fbga package. table 1.4.1 lists pin assignments of the 240qfp. table 1.4.2 lists pin assignments of the 255fbga. figure 1.4.1 pin layout diagram of the 240qfp (top view) package: 240p6y-a (0.5 mm pitch) note: use caution when using these pins because they have a debug event function. m32170f3vfp m32170f4vfp m32170f6vfp 2 4 3 44 43 5 6 7 8 9 35 36 37 38 39 40 22 23 24 25 26 27 28 29 30 31 32 33 34 11 12 13 14 15 16 17 18 19 20 21 41 42 10 1 60 59 51 52 53 54 55 56 45 46 47 48 49 50 57 58 89 90 99 98 97 96 95 94 93 92 91 103 102 101 112 111 110 109 108 107 106 105 104 120 119 118 117 116 115 114 113 63 64 66 67 68 69 70 71 72 73 74 65 84 75 76 77 78 79 80 81 82 83 85 86 87 88 61 62 100 124 132 130 129 127 121 137 146 145 144 143 142 141 140 139 138 155 154 153 152 151 150 149 148 147 156 159 158 157 133 136 135 134 123 122 131 128 126 125 166 165 164 163 162 161 175 174 173 172 171 170 169 168 167 176 179 178 177 160 180 195 185 184 183 182 181 186 189 188 187 194 193 192 191 190 196 199 198 197 205 204 203 202 201 200 206 209 208 207 215 214 213 212 211 210 216 239 217 219 218 225 224 223 222 221 220 226 227 229 228 230 235 234 233 232 231 236 237 238 240 p41/blw/ble p157/tin7 p156/tin6 p155/tin5 p154/tin4 p153/tin3 p152/tin2 p151/tin1 p150/tin0 p147/tin15 p146/tin14 p145/tin13 p144/tin12 p143/tin11 p142/tin10 p141/tin9 p140/tin8 vss vcce p137/tin23 p136/tin22 p135/tin21 p134/tin20 p133/tin19 p132/tin18 p131/tin17 p130/tin16 vss vcci p42/bhw/bhe p127/tclk3 p126/tclk2 p125/tclk1 p124/tclk0 p107/to15 p106/to14 p105/to13 p104/to12 vss vcci p103/to11 vss vcci p43/rd p44/cs0 p45/cs1 p14/db12 p37/a22 p36/a21 p33/a18 p31/a16 p30/a15 p35/a20 p34/a19 p32/a17 vcce p27/a30 p25/a28 p26/a29 p24/a27 p07/db7 p02/db2 p01/db1 p00/db0 p23/a26 p22/a25 p20/a23 p10/db8 p11/db9 vss p15/db13 p13/db11 p12/db10 p06/db6 p04/db4 p03/db3 p47/a14 p21/a24 p46/a13 vcce vss p16/db14 p17/db15 p82/txd0 vss vcce p172/tin24 p173/tin25 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 p160/to21 p161/to22 p162/to23 p163/to24 p164/to25 p165/to26 p166/to27 p167/to28 vss vcci vref0 avcc0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 avss0 p181/to30 p182/to31 p183/to32 p184/to33 p180/to29 vss vcce p186/to35 p187/to36 p190/tin26 p185/to34 p194/tin30 p195/tin31 p196/tin32 p197/tin33 p191/tin27 p192/tin28 p193/tin29 reset p84/sclki0/sclko0 p83/rxd0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 vss vcce vcci p62 vss fp p67/adtrg p66/sclki5/sclko5 p65/sclki4/sclko4 p94/to17 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk p61 p63 p114/to4 p115/to5 p116/to6 p117/to7 vss vcce mod1 p100/to8 p101/to9 p102/to10 p110/to0 p111/to1 p112/to2 p113/to3 p95/to18 p96/to19 p97/to20 p70/bclk/wr p71/wait p72/ hreq p64/sbi mod0 p93/to16 p73/ hack vcci vss vdd fvcc p201/rxd4 p202/txd5 p203/rxd5 p200/txd4 ad1in5 ad1in4 ad1in3 ad1in2 ad1in1 ad1in0 vref1 ad1in15 ad1in14 ad1in13 ad1in12 avss1 ad1in6 jtdo jtrst jtck jtms jtdi p212/to39 p213/to40 p214/to41 p215/to42 p211/to38 p210/to37 p216/to43 p217/to44 vcnt osc-vcc xout xin osc-vss p221/crx p220/ctx vss vss p05/db5 ad1in11 ad1in10 ad1in9 ad1in8 ad1in7 p222 p223 (note) p224/a11 (note) p225/a12 vss avcc1
1 1-19 ver.0.10 overview 1.4 pin layout table 1.4.1 pin assignments of the 240qfp (1/2) no. pin name no. pin name no. pin name no. pin name 1 ad1in12 41 p26 / a29 81 vss 121 p87 / sclki1 / sclko1 2 ad1in13 42 p27 / a30 82 p180 / to29 122 p200 / txd4 3 ad1in14 43 p00 / db0 83 p181 / to30 123 p201 / rxd4 4 ad1in15 44 p01 / db1 84 p182 / to31 124 p202 / txd5 5 avss1 45 p02 / db2 85 p183 / to32 125 p203 / rxd5 6 __ p43 / rd 46 p03 / db3 86 p184 / to33 126 vcci 7 ___ p44 / cs0 47 p04 / db4 87 p185 / to34 127 vss 8 ___ p45 / cs1 48 p05 / db5 88 p186 / to35 128 fvcc 9 p46 / a13 49 p06 / db6 89 p187 / to36 129 vss 10 p47 / a14 50 p07 / db7 90 p190 / tin26 130 p61 11 p220 / ctx 51 vcce 91 p191 / tin27 131 p62 12 p221 / crx 52 vss 92 p192 / tin28 132 p63 13 p222 53 p10 / db8 93 p193 / tin29 133 ___ p64 / sbi 14 p223 54 p11 / db9 94 p194 / tin30 134 p65 / sclki4 / sclko4 15 p224 / a11 55 p12 / db10 95 p195 / tin31 135 p66 / sclki5 / sclko5 16 p225 / a12 56 p13 / db11 96 p196 / tin32 136 _____ p67 / adtrg 17 vss 57 p14 / db12 97 p197 / tin33 137 vcci 18 osc-vss 58 p15 / db13 98 vcci 138 vss 19 xin 59 p16 / db14 99 vss 139 vcce 20 xout 60 p17 / db15 100 p160 / to21 140 ___ p70 / bclk / wr 21 osc-vcc 61 vref0 101 p161 / to22 141 ____ p71 / wait 22 vss 62 avcc0 102 p162 / to23 142 ____ p72 / hreq 23 vcnt 63 ad0in0 103 p163 / to24 143 ____ p73 / hack 24 vss 64 ad0in1 104 p164 / to25 144 p74 / rtdtxd 25 p30 / a15 65 ad0in2 105 p165 / to26 145 p75 / rtdrxd 26 p31 / a16 66 ad0in3 106 p166 / to27 146 p76 / rtdack 27 p32 / a17 67 ad0in4 107 p167 / to28 147 p77 / rtdclk 28 p33 / a18 68 ad0in5 108 p172 / tin24 148 p93 / to16 29 p34 / a19 69 ad0in6 109 p173 / tin25 149 p94 / to17 30 p35 / a20 70 ad0in7 110 p174 / txd2 150 p95 / to18 31 p36 / a21 71 ad0in8 111 p175 / rxd2 151 p96 / to19 32 p37 / a22 72 ad0in9 112 p176 / txd3 152 p97 / to20 33 p20 / a23 73 ad0in10 113 p177 / rxd3 153 _____ reset 34 p21 / a24 74 ad0in11 114 vcce 154 mod0 35 p22 / a25 75 ad0in12 115 vss 155 mod1 36 p23 / a26 76 ad0in13 116 p82 / txd0 156 fp 37 vcce 77 ad0in14 117 p83 / rxd0 157 vcce 38 vss 78 ad0in15 118 p84 / sclki0 / sclko0 158 vss 39 p24 / a27 79 avss0 119 p85 / txd1 159 p110 / to0 40 p25 / a28 80 vcce 120 p86 / rxd1 160 p111 / to1
1 1-20 ver.0.10 overview 1.4 pin layout table 1.4.1 pin assignments of the 240qfp (2/2) no. pin name no. pin name no. pin name no. pin name 161 p112 / to2 181 jtms 201 p134 / tin20 221 p156 / tin6 162 p113 / to3 182 jtck 202 p135 / tin21 222 p157 / tin7 163 p114 / to4 183 jtrst 203 p136 / tin22 223 ___ ___ p41 / blw / ble 164 p115 / to5 184 jtdo 204 p137 / tin23 224 ___ ___ p42 / bhw / bhe 165 p116 / to6 185 jtdi 205 vcce 225 vcci 166 p117 / to7 186 p103 / to11 206 vss 226 vss 167 p100 / to8 187 p104 / to12 207 p140 / tin8 227 vref1 168 p101 / to9 188 p105 / to13 208 p141 / tin9 228 avcc1 169 p102 / to10 189 p106 / to14 209 p142 / tin10 229 ad1in0 170 vdd 190 p107 / to15 210 p143 / tin11 230 ad1in1 171 vcci 191 p124 / tclk0 211 p144 / tin12 231 ad1in2 172 vss 192 p125 / tclk1 212 p145 / tin13 232 ad1in3 173 p210 / to37 193 p126 / tclk2 213 p146 / tin14 233 ad1in4 174 p211 / to38 194 p127 / tclk3 214 p147 / tin15 234 ad1in5 175 p212 / to39 195 vcci 215 p150 / tin0 235 ad1in6 176 p213 / to40 196 vss 216 p151 / tin1 236 ad1in7 177 p214 / to41 197 p130 / tin16 217 p152 / tin2 237 ad1in8 178 p215 / to42 198 p131 / tin17 218 p153 / tin3 238 ad1in9 179 p216 / to43 199 p132 / tin18 219 p154 / tin4 239 ad1in10 180 p217 / to44 200 p133 / tin19 220 p155 / tin5 240 ad1in11
1 1-21 ver.0.10 package: 255f7f (0.8 mm pitch) note 1: nc pins (w19, y1) are not internally connected. leave them open. note 2: use caution when using p224/a11 and p225/a12 because they have a debug event function. note 3: 255fbga is currently under development. figure 1.4.2 pin layout diagram of the 255fbga (top view) ab c de f gh jk l mnp rt uv wy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ad1in12 ad1in13 ad1in14 ad1in15 avss1 p43 /rd p44 /cs0 p45 /cs1 p46 /a13 p47 /a14 p220 /ctx p221 /crx p222 p223 p224 /a11 p225 /a12 vss osc- vss xin xout osc- vcc vss vcnt vss p30 /a15 p31 /a16 p32 /a17 p33 /a18 p34 /a19 p35 /a20 trclk trsync p36 /a21 p37 /a22 p20 /a23 p21 /a24 p23 /a26 p22 /a25 vcce vss p24 /a27 p25 /a28 p26 /a29 p27 /a30 p00 /db0 p01 /db1 p02 /db2 p03 /db3 p04 /db4 p05 /db5 p06 /db6 p07 /db7 vcce vss p10 /db8 p11 /db9 p12 /db10 p13 /db11 p14 /db12 p15 /db13 p16 /db14 p17 /db15 vref0 avcc0 ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 ad0in8 ad0in9 ad0in10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 avss0 vcce vss p180 /to29 p181 /to30 p182 /to31 p183 /to32 p184 /to33 p185 /to34 p186 /to35 p187 /to36 p190 /tin26 p191 /tin27 p192 /tin28 p193 /tin29 p194 /tin30 p196 /tin32 p195 /tin31 p197 /tin33 vcci vss p160 /to21 p161 /to22 p162 /to23 p163 /to24 p164 /to25 p165 /to26 p166 /to27 p167 /to28 p172 /tin24 p173 /tin25 p174 /txd2 p175 /rxd2 p176 /txd3 p177 /rxd3 vcce vss p82 /txd0 p87 /sclk1 p84 /sclk0 p85 /txd1 p86 /rxd1 trdata 0 trdata 1 trdata 2 trdata 3 p200 /txd4 p201 /rxd4 p202 /txd5 p203 /rxd5 vcci vss p83 /rxd0 vss p61 p62 fvcc p64 /sbi p65 /sclk4 p66 /sclk5 p63 vcci vss vcce p67 /adtrg p71 /wait p72 /hreq p73 /hack p74/ rtdtxd p75/ rtdrxd p76/ rtdack p77/ rtdclk p93 /to16 p94 /to17 p95 /to18 p96 /to19 p97 /to20 reset mod0 mod1 fp vcce vss p110 /to0 p111 /to1 p112 /to2 p113 /to3 trdata 4 trdata 5 trdata 6 trdata 7 p114 /to4 p115 /to5 p116 /to6 p117 /to7 p100 /to8 p101 /to9 p102 /to10 vdd vcci vss p210 /to37 p211 /to38 p212 /to39 p214 /to41 p215 /to42 p213 /to40 p216 /to43 p217 /to44 jdbi jtck jevent 0 jtrst jevent 1 jtdo jtdi p103 /to11 p104 /to12 p105 /to13 p106 /to14 p107 /to15 p124 /tclk0 p125 /tclk1 p126 /tclk2 p127 /tclk3 vcci vss p130 /tin16 p131 /tin17 p132 /tin18 p133 /tin19 p134 /tin20 p135 /tin21 p136 /tin22 p137 /tin23 vcce vss p140 /tin8 p141 /tin9 p142 /tin10 p143 /tin11 p144 /tin12 p145 /tin13 p146 /tin14 p147 /tin15 p150 /tin0 p151 /tin1 p152 /tin2 p153 /tin3 p154 /tin4 p155 /tin5 p156 /tin6 p157 /tin7 p41 /blw p42 /bhw vcci vss vref1 avcc1 ad1in0 ad1in1 ad1in2 ad1in3 ad1in4 ad1in5 ad1in6 ad1in7 ad1in8 ad1in10 ad1in9 ad1in11 m32170f3vwg M32170F4VWG m32170f6vwg p70 /bclk jtms n.c n.c overview 1.4 pin layout
1 1-22 ver.0.10 table 1.4.2 pin assignments of the 255fbga (1/2) no. pin name no. pin name no. pin name no. pin name a1 c1 ad1in14 e1 p220 / ctx h1 vcnt a2 ad1in9 c2 ad1in13 e2 ______ p47 / a14 h2 vss a3 ad1in8 c3 ad1in4 e3 _____ p46 / a13 h3 osc-voc a4 ad1in6 c4 ad1in5 e4 _____ p45 / cs1 h4 xout a5 ad1in2 c5 ad1in1 e17 p101 / to9 h17 p111 / to1 a6 verf1 c6 vss e18 vcci h18 trdata4 a7 _______ p41 / blw c7 p157 / tin7 e19 vdd h19 p113 / to3 a8 p154 / tin4 c8 p153 / tin3 e20 p102 / to10 h20 p112 / to2 a9 p150 / tin0 c9 p147 / tin15 f1 p224 / a11 j1 p32 / a17 a10 p144 / tin12 c10 p143 / tin11 f2 p223 j2 p31 / a16 a11 p140 / tin8 c11 p141 / tin9 f3 p222 j3 p30 / a15 a12 p136 / tin22 c12 p137 / tin23 f4 p221 / crx j4 vss a13 p132 / tin18 c13 p133 / tin19 f17 p115 / to5 j17 fp a14 vcci c14 vss f18 p100 / to8 j18 p110 / to0 a15 p124 / tclk0 c15 p125 / tclk1 f19 p117 / to7 j19 vss a16 p104 / to12 c16 p105 / to13 f20 p116 / to6 j20 vcce a17 jevent1 c17 jtdo g1 xin k1 trclk a18 jevent0 c18 p213 / to40 g2 osc-vss k2 p35 / a20 a19 jtck c19 p215 / to42 g3 vss k3 p34 / a19 a20 jtms c20 p214 / to41 g4 p225 / a12 k4 p33 / a18 b1 ad1in12 d1 _________ p44 / cs0 g17 tradata5 k17 p97 / to20 b2 ad1in11 d2 _____ p43 / rd g18 p114 / to4 k18 mod1 b3 ad1in10 d3 avss1 g19 tradata7 k19 mod0 b4 ad1in7 d4 ad1in15 g20 tradata6 k20 ____________ reset b5 ad1in3 d5 ad1in0 b6 avcc1 d6 vcci b7 ________ p42 / bhw d7 p156 / tin6 b8 p155 / tin5 d8 p152 / tin2 b9 p151 / tin1 d9 p146 / tin14 b10 p145 / tin13 d10 p142 / tin10 b11 vss d11 vcce b12 p135 / tin21 d12 p134 / tin20 b13 p131 / tin17 d13 p130 / tin16 b14 p127 / tclk3 d14 p126 / tclk2 b15 p102 / to15 d15 p106 / to4 b16 p103 / to11 d16 jtdi b17 jtrst d17 vss b18 jdbi d18 p212 / to39 b19 p217 / to44 d19 p211 / to38 b20 p216 / to43 d20 p210 / to37 overview 1.4 pin layout
1 1-23 ver.0.10 table 1.4.2 pin assignments of the 255fbga (2/2) no. pin name no. pin name no. pin name no. pin name l1 p36 / a21 p1 p00 / db0 u1 p12 / db10 w1 p16 / db14 l2 p37 / a22 p2 p01 / db1 u2 p13 / db11 w2 vref0 l3 p20 / a23 p3 p02 / db2 u3 p14 / db12 w3 ad0in0 l4 trsync p4 p27 / a30 u4 p11 / db9 w4 ad0in3 l17 p93 / to16 p17 ______ p67 / adtrg u5 ad0in6 w5 ad0in7 l18 p94 / to17 p18 vcci u6 ad0in10 w6 ad0in11 l19 p95 / to18 p19 vss u7 ad0in14 w7 ad0in15 l20 p96 / to19 p20 vcce u8 vss w8 p180 / to29 m1 p22 / a25 r1 p04 / db4 u9 p183 / to32 w9 p184 / to33 m2 p23 / a26 r2 p05 / db5 u10 p187 / to36 w10 p190 / tin26 m3 vcce r3 p06 / db6 u11 p193 / tin29 w11 p196 / tin32 m4 p21 / a24 r4 p03 / db3 u12 p197 / tin33 w12 p160 / to21 m17 p74 / rtdtxd r17 p63 u13 p161 / to22 w13 p164 / to25 m18 p75 / rtdrxd r18 ___ p64 / sbi u14 p165 / to26 w14 p172 / tin24 m19 p76 / rtdack r19 p65 / sclk4 u15 p173 / tin25 w15 p176 / txd3 m20 p77 / rtdclk r20 p66 / sclk5 u16 p177 / rxd3 w16 p82 / txd0 n1 p24 / a27 t1 vcce u17 p83 / rxd0 w17 p86 / rxd1 n2 p25 / a28 t2 vss u18 p203 / rxd5 w18 trdata2 n3 p26 / a29 t3 p10 / db8 u19 vcci w19 n.c n4 vss t4 p07 / db7 u20 vss w20 p201 / rxd4 n17 p70 / bclk t17 fvcc v1 p15 / db13 y1 n.c n18 _____ p71 / wait t18 vss v2 p17 / db15 y2 avcc0 n19 _____ p72 / hreq t19 p61 v3 ad0in1 y3 ad0in2 n20 _____ p73 / hack t20 p62 v4 ad0in5 y4 ad0in4 v5 ad0in9 y5 ad0in8 v6 ad0in13 y6 ad0in12 v7 vcce y7 avss0 v8 p182 / to31 y8 p181 / to30 v9 p186 / to35 y9 p185 / to34 v10 p192 / tin28 y10 p191 / tin27 v11 p194 / tin30 y11 p195 / tin31 v12 vcci y12 vss v13 p162 / to23 y13 p163 / to24 v14 p166 / to27 y14 p167 / to28 v15 p174 / txd2 y15 p175 / rxd2 v16 vcce y16 vss v17 p84 / sclk0 y17 p85 / txd1 v18 p87 / sclk1 y18 trdata0 v19 p200 / txd4 y19 trdata1 v20 p202 / txd5 y20 trdata3 overview 1.4 pin layout
1 1-24 ver.0.10 overview 1.4 pin layout j this is a blank page. j
chapter 2 chapter 2 cpu 2.1 cpu registers 2.2 general-purpose registers 2.3 control registers 2.4 accumulator 2.5 program counter 2.6 data formats
2 2-2 ver.0.10 cpu 2.1 cpu registers 2.1 cpu registers the m32r has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. the accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 general-purpose registers general-purpose registers are 32 bits in width and there are sixteen of them (r0 to r15), which are used to hold data and base addresses. especially, r14 is used as a link register, and r15 is used as a stack pointer. the link register is used to store the return address when executing a subroutine call instruction. the stack pointer is switched between an interrupt stack pointer (spi) and a user stack pointer (spu) depending on the value of the processor status word register (psw)'s stack mode (sm) bit. 31 31 00 r8 r9 r10 r11 r12 r13 r14 (link register) r15 (stack pointer) (note) note: the stack pointer is switched between an interrupt stack pointer (spi) and a user stack pointer (spu) depending on the value of the psw's sm bit. r0 r1 r2 r3 r4 r5 r6 r7 figure 2.2.1 general-purpose registers
2 2-3 ver.0.10 cpu 2.3 control registers 2.3 control registers there are five control registers-processor status word register (psw), condition bit register (cbr), interrupt stack pointer (spi), user stack pointer (spu), and backup pc (bpc). dedicated "mvtc" and "mvfc" instructions are used to set and read these control registers. figure 2.3.1 control registers control registers cr0 cr1 cr2 cr3 0 31 psw cbr spi spu processor status word register condition bit register interrupt stack pointer user stack pointer bpc cr6 backup pc crn notes 1: crn (n = 0-3, 6) denotes control register numbers. 2: dedicated "mvtc" and "mvfc" instructions are used to set and read the control registers.
2 2-4 ver.0.10 cpu 2.3 control registers 2.3.1 processor status word register: psw (cr0) the processor status word register (psw) is used to indicate the status of the m32r. it consists of a regularly used psw field and a special bpsw field which is used to save the psw field when an eit occurs. the psw field consists of several bits labeled stack mode (sm), interrupt enable (ie), and condition bit (c). the bpsw field consists of backup bits of the foregoing, i.e., backup sm bit (bsm), backup ie bit (bie), and backup c bit (bc). d bit name function initial r w 16 bsm (backup sm) holds the value of sm bit when eit indeterminate is accepted. 17 bie (backup ie) holds the value of ie bit when eit indeterminate is accepted. 23 bc (backup c) holds the value of c bit when eit indeterminate is accepted. 24 sm (stack mode) 0: interrupt stack pointer is used. 0 1: user stack pointer is used. 25 ie (interrupt enable) 0: no interrupt is accepted. 0 1: interrupt is accepted. 31 c (condition bit) depending on instruction execution, it indicates 0 whether operation resulted in a carry, borrow, or overflow. notes 1: "initial" shows the state immediately after reset, r = o means the register is readable, w = o means the register is writable. 2: for changes of the state of each bit when an eit event occurs, refer to chapter 4, "eit. (note 1) 16 17 23 24 25 31(lsb) 15 8 7 0(msb) sm ie c bc bsm bie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psw bpsw field psw field
2 2-5 ver.0.10 cpu 2.3 control registers 2.3.2 condition bit register: cbr (cr1) the condition bit register (cbr) is created as a separate register from the psw by extracting the condition bit (c) from it. the value written to the psw c bit is reflected in this register. this register is a read-only register (writes to this register by "mvtc" instruction are ignored). 2.3.3 interrupt stack pointer: spi (cr2) user stack pointer: spu (cr3) the interrupt stack pointer (spi) and user stack pointer (spu) hold the current address of the stack pointer. these registers can be accessed as general-purpose register r15. in this case, whether r15 is used as spi or as spu depends on the psw's stack mode (sm) bit. 2.3.4 backup pc: bpc (cr6) the backup pc (bpc) is a register used to save the value of the program counter (pc) when an eit occurs. bit 31 is fixed to 0. when an eit occurs, the value held in the pc immediately before the eit occurred or the value of the next instruction is set in this register. when the "rte" instruction is executed, the saved value is returned from the bpc to the pc. however, the two low-order bits of the pc when thus returned are always fixed to "00" (control always returns to word boundaries.) spi spi spu spu 0(msb) 0(msb) 31(lsb) 31(lsb) cbr 0(msb) 31(lsb) 0000000000000000000000000000000 c bpc bpc 0 31(lsb) 0(msb)
2 2-6 ver.0.10 2.4 accumulator the accumulator (acc) is a 56-bit register used by dsp function instructions. when read out or written to, it is handled as a 64-bit register. when reading, the value of bit 8 is sign-extended. when writing, bits 0--7 are ignored. also, the accumulator is used by the multiplication instruction "mul." note that when executing this instruction, the value of the accumulator is destroyed. the "mvtachi" and "mvtaclo" instructions are used to write to the accumulator. the "mvtachi" instruction writes data to the 32 high-order bits (bits 0-31), and the "mvtaclo" instruction writes data to the 32 low-order bits (bits 32-63). the "mvfachi," "mvfaclo," and "mvfacmi" instructions are used to read data from the accumulator. the "mvfachi" instruction reads data from the 32 high-order bits (bits 0-31), the "mvfaclo" instruction reads data from the 32 low-order bits (bits 32-63), and the "mvfachi" instruction reads data from the 32 middle bits (bits 16-47). cpu 2.4 accumulator note: bits 0-7 always show the sign-extended value of bit 8. writes to this bit field are ignored. pc pc 0 31(lsb) 0(msb) 2.5 program counter the program counter (pc) is a 32-bit counter used to hold the address of the currently executed instruction. because m32r instructions each start from an even address, the lsb (bit 31) is always 0. 32 48 63(lsb) 31 16 15 0(msb) 47 78 range of bits read by mvfacmi instruction range of bits read/written to by mvfachi/mvtachi instructions range of bits read/written to by mvfaclo/mvtaclo instructions acc (note)
2 2-7 ver.0.10 2.6 data formats 2.6.1 data types there are several data types that can be handled by the m32r's instruction set. these include signed and unsigned 8, 16, and 32-bit integers. values of signed integers are represented by 2's complements. figure 2.6.1 data types cpu 2.6 data formats signed byte (8-bit) integer unsigned byte (8-bit) integer signed halfword (16-bit) integer unsigned halfword (16-bit) integer signed word (32-bit) integer unsigned word (32-bit) integer 0(msb) 0(msb) 0(msb) 0(msb) 0(msb) 0(msb) 7(lsb) 7(lsb) 15(lsb) 15(lsb) 31(lsb) 31(lsb) s s s s : sign bit
2 2-8 ver.0.10 cpu 2.6 data formats 2.6.2 data formats (1) data formats in register data sizes in m32r registers are always words (32 bits). when loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (ldb, ldh instructions) or zero-extended (ldub, lduh instructions) into word (32-bit) data before being stored in the register. when storing data from m32r register into memory, the register data is stored in memory in different sizes depending on the instructions used. the st instruction stores the entire 32-bit data of the register, the sth instruction stores the least significant 16-bit data, and the stb instruction stores the least significant 8-bit data. figure 2.6.2 data formats in register rn 0(msb) 31(lsb) byte rn 0(msb) 31(lsb) halfword rn 0(msb) 31(lsb) word sign-extended (ldb instruction) or zero-extended (ldub instruction) from memory (ldb, ldub instructions) rn 0(msb) 31(lsb) byte rn 0(msb) 31(lsb) halfword rn 0(msb) 31(lsb) word to memory (stb instruction) to memory (sth instruction) to memory (st instruction) from memory (ldh, lduh instructions) from memory (ld instructions) sign-extended (ldh instruction) or zero-extended (lduh instruction) 24 16 24 16
2 2-9 ver.0.10 (2) data formats in memory data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). byte data can be located at any address. however, halfword data must be located at halfword boundaries (where the lsb address bit = "0"), and word data must be located at word boundaries (where two lsb address bits = "00"). if an attempt is made to access memory data across these halfword or word boundaries, an address exception is generated. figure 2.6.3 data formats in memory cpu 2.6 data formats address byte halfword word + 0 address + 1 address + 2 address + 3 address 031 byte 7 8 15 16 23 24 (msb) (lsb) (msb) (lsb) byte byte byte halfword halfword word
2 2-10 ver.0.10 cpu 2.6 data formats (3) endian the following shows the generally used endian methods and the m32r family endian. figure 2.6.4 endian methods figure 2.6.5 m32r family endian bit endian byte endian big endian little endian note: even for bit big endian, h'01 is not b'10000000. (h'01) (h'01234567) msb lsb hh hl lh ll h'01 h'23 h'45 h'67 msb lsb ll lh hl hh h'67 h'45 h'23 h'01 msb lsb b'0000001 d0 d7 msb lsb b'0000001 d7 d0 little/little ll lh hl hh big/big hh hl lh ll little/big hh hl lh ll endian (bit/byte) data arrangement mpu name 7700 family m16c family competition m32r family m16 family 7-0 31-24 15-8 23-16 0-7 24-31 8-15 16-23 bit number +0 +1 +2 +3 +0 +1 +2 +3 +0 +1 +2 +3 address msb lsb msb lsb msb lsb ex:0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 note: the m32r's endian method is big endian for both bit and byte. 7-0 31-24 15-8 23-16
2 2-11 ver.0.10 (4) transfer instructions figure 2.6.6 transfer instructions cpu 2.6 data formats ?constant transfer ld24 rdest, #imm24 ldi rdest, #imm16 ldi rdest, #imm8 seth rdest, #imm16 23 0 rdest imm24 31 0 ld24 rdest, #imm24 15 0 rdest imm16 31 0 seth rdest, #imm16 00 8 15 00 00 ?register to register transfer mv rdest, rsrc ?control register transfer mvfc rdest, crsrc mvtc rsrc, crdest note: for the mvtc instruction, the condition bit c does not change unless crdest is cr0 (psw). rsrc 31 0 rdest 31 0 rsrc 31 0 crdest 31 0 mvtc rsrc, crdest mv rdest, rsrc
2 2-12 ver.0.10 (5) memory (signed) to register transfer figure 2.6.7 memory (signed) to register transfer (6) memory (unsigned) to register transfer figure 2.6.8 memory (unsigned) to register transfer ?signed 32 bits ld24 rsrc, #label ld rdest, @rsrc ?signed 16 bits ld24 rsrc, #label ldh rdest, @rsrc ?signed 8 bits ld24 rsrc, #label ldb rdest, @rsrc label rdest 31 0 +0 +1 +2 +3 rdest label 00 00 ff ff check the msb 0 = positive 1 = negative 31 0 +0 +1 +2 +3 rdest label 00 00 00 ff ff ff 31 0 +0 +1 +2 +3 memory register check the msb 0 = positive 1 = negative ?unsigned 32 bits ld24 rsrc, #label ld rdest, @rsrc ?unsigned 16 bits ld24 rsrc, #label ldub rdest, @rsrc ?unsigned 8 bits ld24 rsrc, #label lduh rdest, @rsrc rdest 00 00 31 0 label +0 +1 +2 +3 label +0 +1 +2 +3 rdest 31 0 label +0 +1 +2 +3 rdest 00 00 00 31 0 memory register cpu 2.6 data formats
2 2-13 ver.0.10 (7) things to be noted for data transfer note that in data transfer, data arrangements in registers and those in memory are different. figure 2.6.9 difference in data arrangements data in memory data in register word data (32 bits) +0 +1 +2 +3 d0 d31 hh hl lh ll d0 d31 hh hl lh ll half-word data (16 bits) +0 +1 +2 +3 d0 d31 h l d0 d15 h l byte data (8 bits) +0 +1 +2 +3 d0 d31 d0 d7 msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb (r0-r15) (r0-r15) (r0-r15) cpu 2.6 data formats
2 2-14 ver.0.10 j this is a blank page. j
chapter 3 chapter 3 address space 3.1 outline of address space 3.2 operation modes 3.3 internal rom area and extended external area 3.4 internal ram area and sfr area 3.5 eit vector entry 3.6 icu vector table 3.7 note about address space
3 3-2 ver.0.10 3.1 outline of address space the m32r's logical addresses are always handled in 32 bits, providing 4 gbytes of linear ad- dress space. the m32r/e's address space consists of the following: (1) user space ? internal rom area ? extended external area ? internal ram area ? special function register (sfr) area (2) boot program space (3) system space (areas not open to the user) (1) user space a 2 gbytes of address space from h'0000 0000 to h'7fff ffff is the user space. located in this space are the internal rom area, extended external area, internal ram area, and spe- cial function register (sfr) area, an area containing a group of internal peripheral i/o regis- ters. of these, the internal rom and extended external areas are located differently depend- ing on mode settings which will be described later. (2) boot program space a 1 gbyte of address space from h'8000 0000 to h'bfff ffff is the boot program space. this space stores a program (boot program) which enables on-board programming when the internal flash area is blank. (3) system space a 1 gbyte of address space from h'c000 0000 to h'ffff ffff is the system space. this space is reserved for use by development tools such as an in-circuit emulator or a debug monitor, and cannot be used by the user. address space 3.1 outline of address space
3 3-3 ver.0.10 address space 3.1 outline of address space figure 3.1.1 address space of the m32170f6 notes1: this location varies with chip mode settings. 2: the boot program space can read out only when fp = 1, mod0 = 1, and mod1 = 0. boot rom area (8 kbytes) h'0000 0000 h'ffff ffff h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16 mbytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16 kbytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area (768 kbytes) (note 1) extended external area (4 mbytes) ghost area in units of 128 kbytes 1 gbyte 1 gbyte 2 gbytes ghost area in units of 16 mbytes ghost area in 4 mbytes internal ram area (40 kbytes) h'0080 dfff h'8000 0000 h'8000 1fff ghost area in units of 16 mbytes reserved area (8 kbytes) aaaa a aa a a aa a aaaa reserved area (72 kbytes) h'0081 ffff h'0082 0000 h'0080 e000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'000b ffff h'0010 0000 cs1 area cs0 area reserved area (256 kbytes) h'000f ffff
3 3-4 ver.0.10 address space 3.1 outline of address space figure 3.1.2 address space of the m32170f4 boot rom area (8 kbytes) h'0000 0000 h'ffff ffff h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16 mbytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16 kbytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area (512 kbytes) (note 1) extended external area (4 mbytes) ghost area in units of 128 kbytes 1 gbyte 1 gbyte 2 gbytes ghost area in units of 16 mbytes ghost area in 4 mbytes internal ram area (32 kbytes) h'0080 bfff h'8000 0000 h'8000 1fff ghost area in units of 16 mbytes reserved area (8 kbytes) aaaa a aa a a aa a aaaa reserved area (80 kbytes) h'0081 ffff h'0082 0000 h'0080 c000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0007 ffff h'0010 0000 cs1 area cs0 area reserved area (512 kbytes) h'000f ffff notes1: this location varies with chip mode settings. 2: the boot program space can read out only when fp = 1, mod0 = 1, and mod1 = 0.
3 3-5 ver.0.10 address space 3.1 outline of address space figure 3.1.3 address space of the m32170f3 boot rom area (8 kbytes) h'0000 0000 h'ffff ffff h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16 mbytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16 kbytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area (384 kbytes) (note 1) extended external area (4 mbytes) ghost area in units of 128 kbytes 1 gbyte 1 gbyte 2 gbytes ghost area in units of 16 mbytes ghost area in 4 mbytes internal ram area (32 kbytes) h'0080 bfff h'8000 0000 h'8000 1fff ghost area in units of 16 mbytes reserved area (8 kbytes) aaaa a aa a a aa a aaaa reserved area (80 kbytes) h'0081 ffff h'0082 0000 h'0080 c000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0005 ffff h'0010 0000 cs1 area cs0 area reserved area (640 kbytes) h'000f ffff notes1: this location varies with chip mode settings. 2: the boot program space can read out only when fp = 1, mod0 = 1, and mod1 = 0.
3 3-6 ver.0.10 3.2 operation modes the 32170 is placed in one of the following modes by setting its operation mode (using mod0 and mod1 pins). for details about the mode used to rewrite the internal flash memory, refer to section 6.5, "programming of internal flash memory." table 3.2.1 setting operation modes mod0 mod1 (note 1) operation mode (note 2) vss vss single-chip mode vss vcc extended external mode vcc vss processor mode (fp = vss) vcc vcc reserved (cannot be used) notes 1: vcc connects to +5 v, and vss connects to gnd. 2: for flash rewrite mode (fp = vcc) not listed in the above table, refer to section 6.5, "programming of internal flash memory." the internal rom and extended external areas are located differently depending on the 32170's operation mode. (all other areas in address space are located the same way.) the address maps of internal rom and extended external areas in each mode are shown below. (for flash rewrite mode (fp = vcc) not listed in the above table, refer to section 6.5, "programming of internal flash memory.") address space 3.2 operation modes figure 3.2.1 m32170f6 operation mode and internal rom/extended external areas h'0000 0000 h'000b ffff h'000c 0000 h'003f ffff non-cs0 area cs1 area (2 mbytes) cs0 area (2 mbytes) cs1 area (2 mbytes) internal rom area (768 kbytes) extended external area extended external area internal rom area (768 kbytes) h'000f ffff h'0010 0000 h'001f ffff h'0020 0000 cs0 area (1 mbyte) reserved area (256 kbytes)
3 3-7 ver.0.10 figure 3.2.2 m32170f4 operation mode and internal rom/extended external areas figure 3.2.3 m32170f3 operation mode and internal rom/extended external areas h'0000 0000 h'0007 ffff h'0008 0000 h'003f ffff non-cs0 area cs1 area (2 mbytes) cs0 area (2 mbytes) cs1 area (2 mbytes) internal rom area (512 kbytes) extended external area extended external area internal rom area (512 kbytes) h'000f ffff h'0010 0000 h'001f ffff h'0020 0000 cs0 area (1 mbyte) reserved area (512 kbytes) h'0000 0000 h'0005 ffff h'0006 0000 h'003f ffff non-cs0 area cs1 area (2 mbytes) cs0 area (2 mbytes) cs1 area (2 mbytes) internal rom area (384 kbytes) extended external area extended external area internal rom area (384 kbytes) h'000f ffff h'0010 0000 h'001f ffff h'0020 0000 cs0 area (1 mbyte) reserved area (640 kbytes) address space 3.2 operation modes
3 3-8 ver.0.10 3.3 internal rom area and extended external area the 8 mbyte area at addresses h'0000 0000 to h'007f ffff in the user space accommodates the internal rom and extended external areas. of this, a 4 mbytes of address space from h'0000 0000 to h'0003 ffff is the area that the user can actually use. all other areas here comprise a 4 mbytes of ghost area. (when programming, do not use this ghost area intentionally.) for details on how the internal rom and extended external areas are located differently depending on the 32170's operation modes set, refer to section 3.2, "operation modes." 3.3.1 internal rom area the internal rom is located in the area shown below. also, this area has an eit vector entry (and icu vector table) located in it at the beginning. table 3.3.1 addresses at which the 32170's internal rom is located type name size located address mf32170f6 768 kbytes h'0000 0000 - h'000b ffff mf32170f4 512 kbytes h'0000 0000 - h'0007 ffff mf32170f3 384 kbytes h'0000 0000 - h'0005 ffff 3.3.2 extended external area an extended external area is provided only when extended external mode or processor mode has been selected when setting the 32170's operation mode. for access to this extended external area, the 32170 outputs the control signals necessary to access external devices. ________ _______ the 32170's cs0 and cs1 signals are output corresponding to the address mapping of the ex- ________ _______ tended external area. the cs0 signal is output for the cs0 area, and the cs1 signal is output for the cs1 area. table 3.3.2 address mapping of the extended external area in each operation mode of the 32170 operation mode address mapping of the extended external area single-chip mode none extended external mode addresses h'0010 0000 to h'001f ffff (cs0 area: 1 mbytes) addresses h'0020 0000 to h'003f ffff (cs1 area: 2 mbytes) processor mode addresses h'0000 0000 to h'001f ffff (cs0 area: 2 mbytes) addresses h'0020 0000 to h'003f ffff (cs1 area: 2 mbytes) address space 3.3 internal rom/extended external area
3 3-9 ver.0.10 3.4 internal ram area and sfr area the 8 mbyte area at addresses h'0080 0000 to h'00ff ffff in the user space accommodates the internal ram area and special function register (sfr) area. of this, a 128 kbytes of address space from h'0080 0000 to h'0081 ffff is the area that the user can actually use. all other areas here comprise a ghost area in units of 128 kbytes. (when programming, do not use this ghost area intentionally.) 3.4.1 internal ram area the internal ram is located in the area shown below. table 3.4.1 addresses at which the 32170's internal rom is located type name size located address mf32170f6 40 kbytes h'0080 4000 - h'0080 dfff mf32170f4 32 kbytes h'0080 4000 - h'0080 bfff mf32170f3 3.4.2 special function register (sfr) area addresses h'0080 0000 to h'0080 3ffff are the special function register (sfr) area. this area has registers for internal peripheral i/o located in it. address space 3.4 internal rom/sfr area figure 3.4.1 internal ram area and special function register (sfr) area of the m32170f6 h'0080 0000 h'0080 dfff sfr area (16 kbytes) internal ram (40 kbytes) h'0080 3fff h'0080 4000 pseudo-flash emulation areas separated in units of 8 kbytes or 4 kbytes can be allocated here. for details, refer to section 6.7.
3 3-10 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.2 internal ram area and special function register (sfr) area of the m32170f4 and m32170f3 h'0080 0000 h'0080 bfff sfr area (16 kbytes) internal ram (32 kbytes) h'0080 3fff h'0080 4000 pseudo-flash emulation areas separated in units of 8 kbytes or 4 kbytes can be allocated here. for details, refer to section 6.7.
3 3-11 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.3 outline address mapping of the sfr area h'0080 0000 h'0080 007e h'0080 0180 interrupt controller (icu) h'0080 0080 a-d0 converter h'0080 00ee serial i/o0-3 h'0080 0100 h'0080 0146 wait controller mjt (common part) mjt (top) mjt (tio) mjt (tms) h'0080 0200 h'0080 0240 h'0080 0300 h'0080 03c0 h'0080 03e0 h'0080 03fe note: the real-time debugger (rtd) is designed to be an independent module operated from an external source, and is transparent to the cpu. 0 7 8 15 h'0080 0a00 +0 address +1 address 0 7 8 15 multijunction timer (mjt) flash control h'0080 07e0 h'0080 07f2 h'0080 023e h'0080 02fe mjt (tod0) h'0080 078c h'0080 07de mjt (tid0) h'0080 0790 h'0080 078e multijunction timer (mjt) serial i/o4, 5 h'0080 0a26 h'0080 0a80 a-d1 converter h'0080 0aee mjt (tod1) mjt (tom0) h'0080 0bde h'0080 0c8c h'0080 0cde mjt (tml1) h'0080 0fe0 h'0080 0ffe h'0080 0400 dmac h'0080 0478 can0 h'0080 1000 h'0080 11fe h'0080 0700 input/output port h'0080 0756 h'0080 03be h'0080 03d8 mjt (tml0) h'0080 0b8c mjt (tid1) h'0080 0b8e h'0080 0b90 h'0080 0c8e h'0080 0c90 mjt (tid2) h'0080 0760 h'0080 3ffe +0 address +1 address multijunction timer (mjt)
3 3-12 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.4 register mapping of the sfr area (1) h'0080 0000 h'0080 0002 h'0080 0004 h'0080 0006 h'0080 006c h'0080 006e h'0080 0070 h'0080 0072 h'0080 0074 h'0080 0076 h'0080 0078 h'0080 007a h'0080 007c h'0080 007e h'0080 0080 h'0080 0082 h'0080 0084 h'0080 0086 h'0080 0088 h'0080 008a h'0080 0090 +0 address +1 address interrupt vector register (ivect) d0 d7 d8 d15 interrupt mask register (imask) sbi control register (sbicr) a-d0 conversion interrupt control register (iad0ccr) sio0 transmit interrupt control register (isio0txcr) sio0 receive interrupt control register (isio0rxcr) sio1 receive interrupt control register (isio1rxcr) sio1 transmit interrupt control register (isio1txcr) dma0-4 interrupt control register (idma04cr) mjt output interrupt control register 0 (imjtocr0) mjt output interrupt control register 2 (imjtocr2) mjt output interrupt control register 4 (imjtocr4) mjt output interrupt control register 6 (imjtocr6) mjt input interrupt control register 0 (imjticr0) mjt output interrupt control register 1 (imjtocr1) mjt output interrupt control register 3 (imjtocr3) mjt output interrupt control register 5 (imjtocr5) mjt output interrupt control register 7 (imjtocr7) mjt input interrupt control register 1 (imjticr1) mjt input interrupt control register 2 (imjticr2) mjt input interrupt control register 3 (imjticr3) mjt input interrupt control register 4 (imjticr4) a-d0 single mode register 0 (ad0sim0) a-d0 single mode register 1 (ad0sim1) a-d0 scan mode register 0 (ad0scm0) a-d0 scan mode register 1 (ad0scm1) a-d0 successive approximation register (ad0sar) a-d0 comparate data register (ad0cmp) h'0080 008c h'0080 0092 h'0080 0094 10-bit a-d0 data register 0 (ad0dt0) 10-bit a-d0 data register 1 (ad0dt1) 10-bit a-d0 data register 2 (ad0dt2) 10-bit a-d0 data register 3 (ad0dt3) 10-bit a-d0 data register 4 (ad0dt4) 10-bit a-d0 data register 5 (ad0dt5) 10-bit a-d0 data register 6 (ad0dt6) 10-bit a-d0 data register 7 (ad0dt7) 10-bit a-d0 data register 8 (ad0dt8) 10-bit a-d0 data register 9 (ad0dt9) 10-bit a-d0 data register 10 (ad0dt10) 10-bit a-d0 data register 11 (ad0dt11) 10-bit a-d0 data register 12 (ad0dt12) 10-bit a-d0 data register 13 (ad0dt13) 10-bit a-d0 data register 14 (ad0dt14) 10-bit a-d0 data register 15 (ad0dt15) h'0080 0096 h'0080 0098 h'0080 009a h'0080 009c h'0080 009e h'0080 00a0 h'0080 00a2 h'0080 00a4 h'0080 00a6 h'0080 00a8 h'0080 00aa h'0080 00ac h'0080 00ae h'0080 00d0 address h'0080 0066 h'0080 0068 h'0080 006a rtd interrupt control register (irtdcr) sio2,3 transmit/receive interrupt control register (iso23cr) dma5-9 interrupt control register (idma59cr) tod0 output interrupt control register (itod0cr) tid0 output interrupt control register (itid0cr) 8-bit a-d0 data register 0 (ad08dt0) h'0080 0064 h'0080 0062 h'0080 0060 can0 transmit/receive & error interrupt control register (ican0cr) tid2 output interrupt control register (itid2cr) tml1 input interrupt control register (itml1cr) a-d1 conversion interrupt control register (iad1ccr) sio4,5 transmit/receive interrupt control register (isio45cr) tod1-tom0 output interrupt control register (itom0cr) tid1 output interrupt control register (itid1cr) blank addresses are reserved areas ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-13 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.5 register mapping of the sfr area (2) h'0080 00da h'0080 00dc h'0080 00de h'0080 00e0 h'0080 00e4 h'0080 00e6 h'0080 00e8 h'0080 00ea h'0080 00ec h'0080 00ee h'0080 0100 h'0080 0102 h'0080 0110 h'0080 0112 h'0080 0114 h'0080 0116 h'0080 0120 h'0080 0126 +0 address +1 address d0 d7 d8 d15 h'0080 0122 h'0080 0130 sio1 baud rate register (s1baur) sio0 transmit buffer register (s0txb) sio0 receive buffer register (s0rxb) sio23 interrupt status register (si23stat) 8-bit a-d0 data register 5 (ad08dt5) 8-bit a-d0 data register 6 (ad08dt6) 8-bit a-d0 data register 7 (ad08dt7) 8-bit a-d0 data register 8 (ad08dt8) 8-bit a-d0 data register 9 (ad08dt9) 8-bit a-d0 data register 10 (ad08dt10) 8-bit a-d0 data register 11 (ad08dt11) 8-bit a-d0 data register 12 (ad08dt12) 8-bit a-d0 data register 13 (ad08dt13) 8-bit a-d0 data register 14 (ad08dt14) 8-bit a-d0 data register 15 (ad08dt15) h'0080 0132 h'0080 0134 h'0080 0136 h'0080 0140 h'0080 0142 h'0080 0144 h'0080 0146 h'0080 0180 h'0080 0200 h'0080 0202 h'0080 0210 h'0080 0212 h'0080 0214 address h'0080 00e2 sio03 interrupt mask register (si03mask) sio03 receive interrupt cause select register (si03sel) sio0 transmit control register (s0tcnt) sio0 transmit/receive mode register (s0mod) sio0 receive control register (s0rcnt) h'0080 0124 sio1 baud rate register (s1baur) sio1 transmit buffer register (s1txb) sio1 receive buffer register (s1rxb) sio1 transmit control register (s1tcnt) sio0 transmit/receive mode register (s1mod) sio1 receive control register (s1rcnt) sio2 baud rate register (s2baur) sio2 transmit buffer register (s2txb) sio2 receive buffer register (s2rxb) sio2 transmit control register (s2tcnt) sio2 transmit/receive mode register (s2mod) sio2 receive control register (s2rcnt) sio3 baud rate register (s3baur) sio3 transmit buffer register (s3txb) sio3 receive buffer register (s3rxb) sio3 transmit control register (s3tcnt) sio3 transmit/receive mode register (s3mod) sio3 receive control register (s3rcnt) wait cycles control register (wtccr) h'0080 0204 clock bus & input event bus control register (ckiebcr) prescaler register 0 (prs0) output event bus control register (oebcr) prescaler register 1 (prs1) prescaler register 2 (prs2) tclk input processing control register (tclkcr) tin input processing control register 0 (tincr0) tin input processing control register 1 (tincr1) h'0080 00d2 h'0080 00d4 h'0080 00d6 h'0080 00d8 8-bit a-d0 data register 1 (ad08dt1) 8-bit a-d0 data register 2 (ad08dt2) 8-bit a-d0 data register 3 (ad08dt3) 8-bit a-d0 data register 4 (ad08dt4) blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-14 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.6 register mapping of the sfr area (3) +0 address +1 address d0 d7 d8 d15 h'0080 021e f/f source select register 0 (ffs0) f/f source select register 1 (ffs1) f/f protect register 0 (ffp0) f/f data register 0 (ffd0) h'0080 0220 h'0080 0222 h'0080 0224 h'0080 0226 h'0080 0228 h'0080 022a f/f protect register 1 (ffp1) f/f data register 1 (ffd1) h'0080 0230 h'0080 0232 h'0080 0234 h'0080 0236 h'0080 0238 h'0080 023a h'0080 023c h'0080 023e h'0080 0240 h'0080 0242 h'0080 0244 h'0080 0246 h'0080 0250 top interrupt control register 0 (topir0) top interrupt control register 1 (topir1) top interrupt control register 2 (topir2) tio interrupt control register 0 (tioir0) tio interrupt control register 2 (tioir2) top interrupt control register 3 (topir3) tio interrupt control register 1 (tioir1) tms interrupt control register (tmsir) tin interrupt control register 0 (tinir0) tin interrupt control register 2 (tinir2) tin interrupt control register 4 (tinir4) tin interrupt control register 6 (tinir6) tin interrupt control register 1 (tinir1) tin interrupt control register 3 (tinir3) tin interrupt control register 5 (tinir5) top0 counter (top0ct) top0 reload register (top0rl) top0 correction register (top0cc) top1 counter (top1ct) address h'0080 0252 h'0080 0254 h'0080 0260 h'0080 0262 h'0080 0264 h'0080 0266 top1 reload register (top1rl) top1 correction register (top1cc) h'0080 0256 top2 counter (top2ct) top2 reload register (top2rl) top2 correction register (top2cc) top3 counter (top3ct) top3 reload register (top3rl) top3 correction register (top3cc) h'0080 0270 h'0080 0272 h'0080 0274 h'0080 0276 h'0080 0280 h'0080 0282 h'0080 0284 h'0080 0286 top4 counter (top4ct) top4 reload register (top4rl) top4 correction register (top4cc) top5 counter (top5ct) top5 reload register (top5rl) h'0080 0290 h'0080 0292 h'0080 0294 h'0080 0216 h'0080 021c h'0080 0218 h'0080 021a tin input processing control register 2 (tincr2) tin input processing control register 3 (tincr3) tin input processing control register 4 (tincr4) tin interrupt control register 7 (tinir7) blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-15 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.7 register mapping of the sfr area (4) top5 correction register (top5cc) +0 address +1 address d0 d7 d8 d15 h'0080 029e h'0080 02a0 h'0080 02a2 h'0080 02a4 h'0080 02a6 top6 counter (top6ct) top6 reload register (top6rl) top6 correction register (top6cc) h'0080 02b0 h'0080 02b2 h'0080 02b4 top7 counter (top7ct) top7 reload register (top7rl) top7 correction register (top7cc) h'0080 02c0 h'0080 02c2 h'0080 02c4 h'0080 02c6 top8counter (top8ct) top8 reload register (top8rl) top8 correction register (top8cc) h'0080 02b6 h'0080 02a8 h'0080 02aa top6, 7 control register (top67cr) address h'0080 02d0 h'0080 02d2 h'0080 02d4 h'0080 02d6 top9 counter (top9ct) top9 reload register (top9rl) top9 correction register (top9cc) top10 counter (top10ct) top10 reload register (top10rl) top10 correction register (top10cc) h'0080 02e0 h'0080 02e2 h'0080 02e4 h'0080 02e6 h'0080 02e8 h'0080 02ea top8-10 control register (top810cr) top0-10 external enable register (topeen) top0-10 enable protect register (toppro) top0-10 count enable register (topcen) h'0080 02fa h'0080 02fc h'0080 02fe h'0080 0300 tio0 counter (tio0ct) tio0 reload register (tio0rl) tio0 reload 0/measure register (tio0rl0) tio1 counter (tio1ct) tio1 reload register (tio1rl) tio1 reload 0/measure register (tio1rl0) tio0-3 control register 0 (tio03cr0) h'0080 0302 h'0080 0304 h'0080 0306 h'0080 0310 h'0080 0312 h'0080 0314 h'0080 0316 h'0080 0318 h'0080 031a top0-5 control register 0 (top05cr0) top0-5 control register 1 (top05cr1) h'0080 0296 h'0080 0298 h'0080 029a h'0080 029c blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-16 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.8 register mapping of the sfr area (5) +0 address +1 address d0 d7 d8 d15 h'0080 0324 h'0080 0326 tio2 reload 1 register (tio2rl1) tio2 reload 0/measure register (tio2rl0) h'0080 0330 h'0080 0332 h'0080 0334 h'0080 0336 tio3 counter (tio3ct) tio3 reload 1 register (tio3rl1) tio3 reload 0/measure register (tio3rl0) h'0080 0340 h'0080 0342 h'0080 0344 address tio4 counter (tio4ct) tio4 reload 1 register (tio4rl1) tio4 reload 0/measure register (tio4rl0) tio4 control register (tio4cr) tio5 control register (tio5cr) tio5 counter (tio5ct) tio5 reload 1 register (tio5rl1) tio5 reload 0/measure register (tio5rl0) h'0080 0346 h'0080 0348 h'0080 034a h'0080 0350 h'0080 0352 h'0080 0354 h'0080 0356 tio6 counter (tio6ct) tio6 reload 1 register (tio6rl1) tio6 reload 0/measure register (tio6rl0) tio6 control register (tio6cr) tio7 control register (tio7cr) h'0080 0360 h'0080 0362 h'0080 0364 h'0080 0366 h'0080 0368 h'0080 036a h'0080 0370 h'0080 0372 h'0080 0374 h'0080 0376 tio7 counter (tio7ct) tio7 reload 1 register (tio7rl1) tio7 reload 0/measure register (tio7rl0) h'0080 0380 h'0080 0382 h'0080 0384 h'0080 0386 h'0080 0388 h'0080 038a tio8 counter (tio8ct) tio8 reload 1 register (tio8rl1) tio8 reload 0/measure register (tio8rl0) tio8 control register (tio8cr) tio9 control register (tio9cr) h'0080 0390 h'0080 0392 h'0080 0394 h'0080 0396 tio9 counter (tio9ct) tio9 reload 1 register (tio9rl1) tio9 reload 0/measure register (tio9rl0) tio0-3 control register 1 (tio03cr1) tio2 counter (tio2ct) h'0080 031c h'0080 0320 h'0080 0322 blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-17 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.9 register mapping of the sfr area (6) d0 d7 d8 d15 tms0 counter (tms0ct) tms0 measure 3 register (tms0mr3) tms0 measure 2 register (tms0mr2) tms0 measure 1 register (tms0mr1) h'0080 03c0 h'0080 03c2 h'0080 03c4 h'0080 03c6 tms0 measure 0 register (tms0mr0) tms0 control register (tms0cr) tms1 control register (tms1cr) tms1 counter (tms1ct) tms1 measure 3 register (tms1mr3) tms1 measure 2 register (tms1mr2) tms1 measure 1 register (tms1mr1) tms1 measure 0 register (tms1mr0) h'0080 03c8 h'0080 03ca h'0080 03d0 h'0080 03d2 h'0080 03d4 h'0080 03d6 h'0080 03d8 h'0080 03e0 h'0080 03e2 h'0080 03ea h'0080 03f0 h'0080 03f2 h'0080 03f4 h'0080 03f6 h'0080 03f8 h'0080 03fa h'0080 03fc tml0 counter, high (tml0cth) tml0 counter, low (tml0ctl) tml0 measure 3 register, high (tml0mr3h) tml0 measure 3 register, low (tml0mr3l) tml0 measure 2 register, high (tml0mr2h) tml0 measure 2 register, low (tml0mr2l) tml0 measure 1 register, high (tml0mr1h) tml0 measure 1 register, low (tml0mr1l) tml0 measure 0 register, high (tml0mr0h) tml0 control register (tml0cr) h'0080 03fe tml0 measure 0 register, low (tml0mr0l) dma0-4 interrupt mask register (dm04itmk) dma0 channel control register (dm0cnt) dma0 transfer count register (dm0tct) dma0 source address register (dm0sa) dma0 destination address register (dm0da) dma1 channel control register (dm1cnt) dma1 transfer count register (dm1tct) dma1 source address register (dm1sa) dma1 destination address register (dm1da) h'0080 0412 h'0080 0414 h'0080 0416 h'0080 0418 h'0080 041a h'0080 041c h'0080 0410 h'0080 041e h'0080 0422 h'0080 0424 h'0080 0426 h'0080 0428 h'0080 0420 dma0-4 interrupt request status register (dm04itst) h'0080 0400 h'0080 0408 dma5-9 interrupt mask register (dm59itmk) dma5-9 interrupt request status register (dm59itst) dma5 channel control register (dm5cnt) dma5 transfer count register (dm5tct) dma5 source address register (dm5sa) dma5 destination address register (dm5da) dma6 channel control register (dm6cnt) dma6 transfer count register (dm6tct) h'0080 03be tio0-9 count enable register (tiocen) h'0080 042a h'0080 042c h'0080 042e dma6 source address register (dm6sa) dma6 destination address register (dm6da) h'0080 03bc tio0-9 enable protect register (tiopro) +0 address +1 address address blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-18 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.10 register mapping of the sfr area (7) d0 d7 d8 d15 dma2 channel control register (dm2cnt) dma2 transfer count register (dm2tct) h'0080 0430 h'0080 0432 h'0080 0434 h'0080 0436 h'0080 0438 h'0080 043a h'0080 043c h'0080 043e h'0080 0442 h'0080 0444 h'0080 0446 h'0080 0448 h'0080 044a h'0080 044c h'0080 0440 h'0080 044e h'0080 0450 h'0080 0452 h'0080 0454 h'0080 0456 h'0080 0458 h'0080 045a h'0080 045c h'0080 045e h'0080 0460 h'0080 0464 h'0080 0466 h'0080 0462 dma2 source address register (dm2sa) dma2 destination address register (dm2da) dma3 channel control register (dm3cnt) dma3 transfer count register (dm3tct) dma3 source address register (dm3sa) dma3 destination address register (dm3da) dma4 channel control register (dm4cnt) dma4 transfer count register (dm4tct) dma4 source address register (dm4sa) dma4 destination address register (dm4da) dma0 software request generation register (dm0sri) dma1 software request generation register (dm1sri) dma2 software request generation register (dm2sri) dma3 software request generation register (dm3sri) dma7 channel control register (dm7cnt) dma7 transfer count register (dm7tct) dma7 source address register (dm7sa) dma7 destination address register (dm7da) dma8 channel control register (dm8cnt) dma8 transfer count register (dm8tct) dma8 source address register (dm8sa) dma8 destination address register (dm8da) dma9 channel control register (dm9cnt) dma9 transfer count register (dm9tct) dma9 source address register (dm9sa) dma9 destination address register (dm9da) dma4 software request generation register (dm4sri) dma5 software request generation register (dm5sri) dma6 software request generation register (dm6sri) dma7 software request generation register (dm7sri) dma8 software request generation register (dm8sri) dma9 software request generation register (dm9sri) h'0080 0468 h'0080 0470 h'0080 0474 h'0080 0476 h'0080 0472 h'0080 0478 h'0080 0700 p0 data register (p0data) p1 data register (p1data) p2 data register (p2data) p3 data register (p3data) p4 data register (p4data) p6 data register (p6data) p7 data register (p7data) h'0080 0702 h'0080 0704 h'0080 0706 h'0080 0708 h'0080 070a h'0080 070c p8 data register (p8data) p10 data register (p10data) p12 data register (p12data) p9 data register (p9data) p11data register (p11data) p13 data register (p13data) p20 data register (p20data) p18 data register (p18data) p16 data register (p16data) p14 data register (p14data) h'0080 070e h'0080 0710 h'0080 0712 h'0080 0714 p15 data register (p15data) p17 data register (p17data) p19 data register (p19data) p21 data register (p21data) blank addresses are reserved areas. +0 address +1 address address ~ ~ ~ ~ ~ ~ ~ ~
3 3-19 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.11 register mapping of the sfr area (8) +0 address +1 address d0 d7 d8 d15 p2 direction register (p2dir) p3 direction register (p3dir) p4 direction register (p4dir) p6 direction register (p6dir) p7 direction register (p7dir) p8 direction register (p8dir) p9 direction register (p9dir) p10 direction register (p10dir) p11 direction register (p11dir) p12 direction register (p12dir) p13 direction register (p13dir) p14 direction register (p14dir) p15 direction register (p15dir) h'0080 0724 h'0080 0722 h'0080 0728 h'0080 0726 h'0080 072c h'0080 072a h'0080 0730 h'0080 072e address h'0080 0746 h'0080 074a h'0080 0748 h'0080 074e h'0080 074c p6 operation mode register (p6mod) p7 operation mode register (p7mod) p8 operation mode register (p8mod) p9 operation mode register (p9mod) p10 operation mode register (p10mod) p11 operation mode register (p11mod) p12 operation mode register (p12mod) p13 operation mode register (p13mod) p14 operation mode register (p14mod) p15 operation mode register (p15mod) p16 direction register (p16dir) p17 direction register (p17dir) h'0080 0750 p16 operation mode register (p16mod) p17 operation mode register (p17mod) h'0080 078c tid0 counter (tid0ct) tid0 reload register (tid0rl) h'0080 078e h'0080 0790 tod0_0 counter (tod00ct) tod0_0 reload 1 register (tod00rl1) tod0_0 reload 0 register (tod00rl0) tod0_1 counter (tod01ct) tod0_1 reload 1 register (tod01rl1) tod0_0 reload 0 register (tod01rl0) tod0_2 counter (tod02ct) tod0_2 reload 1 register (tod02rl1) h'0080 0794 h'0080 0792 h'0080 0798 h'0080 0796 h'0080 079c h'0080 079a h'0080 07a0 h'0080 079e h'0080 07a4 h'0080 07a2 h'0080 0744 port input function enable register (pien) p22 data register (p22data) h'0080 0716 h'0080 0720 h'0080 0732 h'0080 0734 h'0080 0736 p18 direction register (p18dir) p20 direction register (p20dir) p22 direction register (p22dir) p19 direction register (p19dir) p21 direction register (p21dir) h'0080 0752 h'0080 0754 h'0080 0756 p18 operation mode register (p18mod) p20 operation mode register (p20mod) p22 operation mode register (p22mod) p19 operation mode register (p19mod) p21 operation mode register (p21mod) bus mode control register (busmodc) p0 direction register (p0dir) p1 direction register (p1dir) h'0080 077e h'0080 07a6 h'0080 07a8 h'0080 07aa tod0_2 reload 0 register (tod02rl0) tod0_3 counter (tod03ct) tod0_3 reload 1 register (tod03rl1) tod0_3 reload 0 register (tod03rl0) h'0080 07ac h'0080 07ae blank addresses are reserved areas. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-20 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.12 register mapping of the sfr area (9) d0 d7 d8 d15 tod0_7 reload 1 register (tod07rl1) h'0080 07cc h'0080 07ca h'0080 07d0 h'0080 07ce h'0080 07d4 h'0080 07d2 h'0080 07d8 h'0080 07d6 h'0080 07de h'0080 07e2 h'0080 07e0 h'0080 07e8 flash mode register (fmod) flash control register 1 (fcnt1) h'0080 07dc h'0080 07da tod0_7 reload 0 register (tod07rl0) prescaler register 3 (prs3) tid0 control & prescaler 3 enable register (tid0pres3en) tod0 interrupt mask register (tod0ima) tod0 interrupt status register (tod0ist) f/f protect register 2 (ffp2) f/f data register 2 (ffd2) tod0 control register (tod0cr) tod0 enable protect register (tod0pro) tod0 count enable register (tod0cen) h'0080 07e4 flash status register 1 (fstat1) flash control register 2 (fcnt2) flash control register 3 (fcnt3) flash control register 4 (fcnt4) tod0_4 counter (tod04ct) tod0_4 reload 1 register (tod04rl1) tod0_4 reload 0 register (tod04rl0) tod0_5 counter (tod05ct) tod0_5 reload 1 register (tod05rl1) tod0_5 reload 0 register (tod05rl0) tod0_6 counter (tod06ct) tod0_6 reload 1 register (tod06rl1) tod0_6 reload 0 register (tod06rl0) tod0_7 counter (tod07ct) h'0080 07b0 h'0080 07b4 h'0080 07b8 h'0080 07b6 h'0080 07bc h'0080 07ba h'0080 07be h'0080 07b2 h'0080 07c0 h'0080 07c4 h'0080 07c8 h'0080 07c6 h'0080 07c2 pseudo-flash l bank register 0 (felbank0) h'0080 07ea h'0080 0a00 h'0080 0a02 h'0080 0a10 h'0080 0a12 h'0080 0a14 h'0080 0a16 h'0080 0a20 h'0080 0a22 h'0080 0a24 pseudo-flash l bank register 1 (felbank1) sio45 interrupt status register (si45stat) sio45 receive interrupt cause select register (si45sel) sio45 interrupt mask register (si45mask) sio4 transmit control register (s4tcnt) sio4 receive control register (s4rcnt) sio4 transmit buffer register (s4txb) sio4 receive buffer register (s4rxb) sio4 transmit/receive mode register (s4mod) sio4 baud rate register (s4baur) sio5 transmit control register (s5rcnt) sio5 transmit/receive mode register (s5mod) sio5 transmit buffer register (s5txb) sio5 receive buffer register (s5rxb) h'0080 07ec pseudo-flash l bank register 2 (felbank2) pseudo-flash l bank register 3 (felbank3) h'0080 0a26 sio5 receive control register (s5rcnt) sio5 baud rate register (s5baur) h'0080 07ee pseudo-flash s bank register 0 (fesbank0) pseudo-flash s bank register 1 (fesbank1) h'0080 07f0 h'0080 07f2 h'0080 07e6 blank addresses are reserved areas. +0 address +1 address address ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-21 ver.0.10 figure 3.4.13 register mapping of the sfr area (10) address space 3.4 internal rom/sfr area d0 d7 d8 d15 10-bit a-d1 data register 9 (ad1dt9) h'0080 0aa2 h'0080 0aa0 h'0080 0aa6 h'0080 0aa4 h'0080 0aaa h'0080 0aa8 h'0080 0aae h'0080 0aac h'0080 0ad2 h'0080 0ad6 h'0080 0ad4 h'0080 0adc h'0080 0ad0 10-bit a-d1 data register 10 (ad1dt10) 8-bit a-d1 data register 0 (ad18dt0) 8-bit a-d1 data register 1 (ad18dt1) h'0080 0ad8 8-bit a-d1 data register 2 (ad18dt2) a-d1 successive approximation register (ad1sar) a-d1 comparate data register (ad1cmp) 10-bit a-d1 data register 1 (ad1dt1) 10-bit a-d1 data register 2 (ad1dt2) 10-bit a-d1 data register 3 (ad1dt3) 10-bit a-d1 data register 5 (ad1dt5) 10-bit a-d1 data register 6 (ad1dt6) 10-bit a-d1 data register 7 (ad1dt7) h'0080 0a82 h'0080 0a80 h'0080 0a84 h'0080 0a86 h'0080 0a8a h'0080 0a8c h'0080 0a92 h'0080 0a90 h'0080 0a94 h'0080 0a88 h'0080 0a96 h'0080 0a9a h'0080 0a9e h'0080 0a9c h'0080 0a98 h'0080 0ade h'0080 0ae2 h'0080 0ae4 h'0080 0ae8 h'0080 0aea h'0080 0aec h'0080 0aee h'0080 0b8c h'0080 0b8e h'0080 0b90 tid1 reload register (tid1rl) tod1_0 counter (tod10ct) a-d1 single mode register 0 (ad1sim0) a-d1 single mode register 1 (ad1sim1) a-d1 scan mode register 0 (ad1scm0) a-d1 scan mode register 1 (ad1scm1) 10-bit a-d1 data register 0 (ad1dt0) 10-bit a-d1 data register 4 (ad1dt4) 10-bit a-d1 data register 8 (ad1dt8) 10-bit a-d1 data register 11 (ad1dt11) 10-bit a-d1 data register 12 (ad1dt12) 10-bit a-d1 data register 13 (ad1dt13) 10-bit a-d1 data register 14 (ad1dt14) 10-bit a-d1 data register 15 (ad1dt15) h'0080 0ada h'0080 0ae0 h'0080 0ae6 8-bit a-d1 data register 3 (ad18dt3) 8-bit a-d1 data register 4 (ad18dt4) 8-bit a-d1 data register 5 (ad18dt5) 8-bit a-d1 data register 6 (ad18dt6) 8-bit a-d1 data register 7 (ad18dt7) 8-bit a-d1 data register 8 (ad18dt8) 8-bit a-d1 data register 9 (ad18dt9) 8-bit a-d1 data register 10 (ad18dt10) 8-bit a-d1 data register 11 (ad18dt11) 8-bit a-d1 data register 12 (ad18dt12) 8-bit a-d1 data register 13 (ad18dt13) 8-bit a-d1 data register 14 (ad18dt14) 8-bit a-d1 data register 15 (ad18dt15) tid1 counter (tid1ct) tod1_0 reload 1 register (tod10rl1) h'0080 0b92 h'0080 0b94 blank addresses are reserved areas. +0 address +1 address address ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-22 ver.0.10 figure 3.4.14 register mapping of the sfr area (11) address space 3.4 internal rom/sfr area +0 address +1 address d0 d7 d8 d15 tod1_5 counter (tod15ct) h'0080 0bb8 h'0080 0bb6 h'0080 0bbc h'0080 0bba h'0080 0bc0 h'0080 0bbe h'0080 0bc4 h'0080 0bc2 h'0080 0bca address h'0080 0bce h'0080 0bcc h'0080 0bd4 h'0080 0bc8 h'0080 0bd0 tod1_1 reload 0 register (tod11rl0) tod1_3 counter (tod13ct) tod1_3 reload 1 register (tod13rl1) tod1_4 counter (tod14ct) tod1_4 reload 1 register (tod14rl1) h'0080 0b98 h'0080 0b96 h'0080 0b9a h'0080 0b9c h'0080 0ba0 h'0080 0ba2 h'0080 0ba8 h'0080 0ba6 h'0080 0baa h'0080 0b9e h'0080 0bac h'0080 0bb0 h'0080 0bb4 h'0080 0bb2 h'0080 0bae h'0080 0bd6 h'0080 0bda h'0080 0bdc h'0080 0c8c h'0080 0c8e h'0080 0c90 h'0080 0c94 h'0080 0c96 h'0080 0c98 tom0_0 reload 0 register (tom00rl0) tom0_1 counter (tom01ct) tod1_2 reload 0 register (tod12rl0) tod1_3 reload 0 register (tod13rl0) tod1_4 reload 0 register (tod14rl0) tod1_5 reload 1 register (tod15rl1) tod1_5 reload 0 register (tod15rl0) tod1_6 counter (tod16ct) tod1_6 reload 1 register (tod16rl1) h'0080 0bd2 h'0080 0bd8 h'0080 0bde tod1 interrupt status register (tod1ist) f/f protect register 3 (ffp3) f/f data register 3 (ffd3) tod1 enable protect register (tod1pro) tod1 count enable register (tod1cen) tom0_0 reload 1 register (tom00rl1) h'0080 0ba4 h'0080 0bc6 h'0080 0c92 tod1_0 reload 0 register (tod10rl0) tod1_1 counter (tod11ct) tod1_1 reload 1 register (tod11rl1) tod1_2 counter (tod12ct) tod1_2 reload 1 register (tod12rl1) tod1_6 reload 0 register (tod16rl0) tod1_7 counter (tod17ct) tod1_7 reload 1 register (tod17rl1) tod1_7 reload 0 register (tod17rl0) tid1 control & prescaler 4 enable register (tid1prs4en) prescaler register 4 (prs4) tod1 interrupt mask register (tod1ima) tod1 control register (tod1cr) tid2 counter (tid2ct) tid2 reload register (tid2rl) tom0_0 counter (tom00ct) h'0080 0c9a h'0080 0c9c tom0_1 reload 1 register (tom01rl1) blank addresses are reserved areas. ~ ~ ~ ~
3 3-23 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.15 register mapping of the sfr area (12) d0 d7 d8 d15 tom0_6 counter (tom06ct) h'0080 0cc0 h'0080 0cbe h'0080 0cc4 h'0080 0cc2 h'0080 0cc8 h'0080 0cc6 h'0080 0ccc h'0080 0cca h'0080 0cd2 h'0080 0cd6 h'0080 0cd4 h'0080 0cdc h'0080 0cd0 h'0080 0cd8 tom0_2 reload 0 register (tom02rl0) tom0_4 counter (tom04ct) tom0_4 reload 1 register (tom04rl1) tom0_5 counter (tom05ct) tom0_5 reload 1 register (tom05rl1) h'0080 0ca0 h'0080 0c9e h'0080 0ca2 h'0080 0ca4 h'0080 0ca8 h'0080 0caa h'0080 0cb0 h'0080 0cae h'0080 0cb2 h'0080 0ca6 h'0080 0cb4 h'0080 0cb8 h'0080 0cbc h'0080 0cba h'0080 0cb6 h'0080 0cde h'0080 0fe0 h'0080 0fe2 h'0080 0ff0 h'0080 0ff2 h'0080 0ff6 h'0080 0ff8 h'0080 0ffa tml1 measure 1 register, high (tml1mr1h) tml1 measure 1 register, low (tml1mr1l) tom0_3 reload 0 register (tom03rl0) tom0_4 reload 0 register (tom04rl0) tom0_5 reload 0 register (tom05rl0) tom0_6 reload 1 register (tom06rl1) tom0_6 reload 0 register (tom06rl0) tom0_7 counter (tom07ct) tom0_7 reload 1 register (tom07rl1) h'0080 0cda tom0 interrupt status register (tom0ist) f/f protect register 4 (ffp4) f/f data register 4 (ffd4) tom0 count enable register (tom0cen) tom0 enable protect register (tom0pro) tml1 measure 2 register, low (tml1mr2l) h'0080 0cac h'0080 0cce h'0080 0ff4 tom0_1 reload 0 register (tom01rl0) tom0_2 counter (tom02ct) tom0_2 reload 1 register (tom02rl1) tom0_3 counter (tom03ct) tom0_3 reload 1 register (tom03rl1) tom0_7 reload 0 register (tom07rl0) tid2 control & prescaler 5 enable register (tid2prs5en) prescaler register 5 (prs5) tom0 interrupt mask register (tom0ima) tom0 control register (tom0cr) tml1 measure 3 register, high (tml1mr3h) tml1 counter, high (tml1cth) tml1 counter, low (tml1ctl) h'0080 0fea tml1 control register (tml1cr) tml1 measure 2 register, high (tml1mr2h) h'0080 0ffc h'0080 0ffe tml1 measure 0 register, high (tml1mr0h) tml1 measure 0 register, low (tml1mr0l) blank addresses are reserved areas. +0 address +1 address address tml1 measure 3 register, low (tml1mr3l) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
3 3-24 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.16 register mapping of the sfr area (13) d0 d7 d8 d15 h'0080 1034 h'0080 1032 h'0080 1038 h'0080 1036 h'0080 103c h'0080 103a h'0080 1054 h'0080 1058 h'0080 1056 h'0080 1052 h'0080 105a can0 configuration register (can0conf) can0 global mask register standard id0 (c0gmsks0) can0 local mask register a standard id0 (c0lmskas0) h'0080 1000 h'0080 1002 h'0080 1004 h'0080 1008 h'0080 100a h'0080 1010 h'0080 100e h'0080 1006 h'0080 1028 h'0080 102c h'0080 1030 h'0080 102e h'0080 102a h'0080 105c h'0080 100c h'0080 1050 can0 control register (can0cnt) can0 extension id register (can0extid) can0 time stamp count register (can0tstmp) can0 slot interrupt status register (can0slist) can0 message slot 3 control register (c0msl3cnt) can0 message slot 2 control register (c0msl2cnt) can0 message slot 4 control register (c0msl4cnt) can0 status register (can0stat) can0 receive error count register (can0rec) can0 transmit error count register (can0tec) can0 message slot 0 control register (c0msl0cnt) can0 message slot 1 control register (c0msl1cnt) can0 message slot 5 control register (c0msl5cnt) can0 message slot 7 control register (c0msl7cnt) can0 message slot 9 control register (c0msl9cnt) can0 message slot 11 control register (c0msl11cnt) can0 message slot 13 control register (c0msl13cnt) can0 message slot 15 control register (c0msl15cnt) can0 message slot 6 control register (c0msl6cnt) can0 message slot 8 control register (c0msl8cnt) can0 message slot 10 control register (c0msl10cnt) can0 message slot 12 control register (c0msl12cnt) can0 message slot 14 control register (c0msl14cnt) h'0080 1012 can0 error interrupt status register (can0erist) can0 error interrupt mask register (can0erimk) h'0080 1014 h'0080 1016 can0 baud rate prescaler (can0brp) h'0080 105e can0 global mask register standard id1 (c0gmsks1) can0 global mask register extended id0 (c0gmske0) can0 global mask register extended id1 (c0gmske1) can0 global mask register extended id2 (c0gmske2) can0 local mask register a standard id1 (c0lmskas1) can0 local mask register a extended id0 (c0lmskae0) can0 local mask register a extended id1 (c0lmskae1) can0 local mask register a extended id2 (c0lmskae2) can0 local mask register b standard id0 (c0lmskbs0) can0 local mask register b standard id0 (c0lmskbs1) can0 local mask register b extended id0 (c0lmskbe0) can0 local mask register b extended id0 (c0lmskbe1) can0 local mask register b extended id0 (c0lmskbe0) blank addresses are reserved areas. +0 address +1 address address can0 slot interrupt mask register (can0slimk) ~ ~ ~ ~ ~ ~ ~ ~
3 3-25 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.17 register mapping of the sfr area (14) d0 d7 d8 d15 h'0080 1102 h'0080 1104 h'0080 110c h'0080 110e h'0080 1112 h'0080 1114 h'0080 1116 h'0080 1110 h'0080 1108 h'0080 1106 h'0080 110a can0 message slot 0 extended id0 (c0msl0eid0) can0 message slot 0 extended id2 (c0msl0eid2) can0 message slot 0 data 0 (c0msl0dt0) can0 message slot 0 data 2 (c0msl0dt2) can0 message slot 0 data 4 (c0msl0dt4) can0 message slot 0 extended id1 (c0msl0eid1) can0 message slot 0 data length register (c0msl0dlc) can0 message slot 0 data 1 (c0msl0dt1) can0 message slot 0 data 3 (c0msl0dt3) can0 message slot 0 data 5 (c0msl0dt5) can0 message slot 0 data 6 (c0msl0dt6) can0 message slot 0 data 7 (c0msl0dt7) can0 message slot 0 time stamp (c0msl0tsp) can0 message slot 1 standard id0 (c0msl1sid0) can0 message slot 1 extended id0 (c0msl1eid0) can0 message slot 1 extended id2 (c0msl1eid2) can0 message slot 1 data 0 (c0msl1dt0) can0 message slot 1 standard id1 (c0msl1sid1) can0 message slot 1 extended id1 (c0msl1eid1) can0 message slot 1 data length register (c0msl1dlc) can0 message slot 1 data 1 (c0msl1dt1) can0 message slot 1 data 3 (c0msl1dt3) can0 message slot 1 data 5 (c0msl1dt5) can0 message slot 1 data 2 (c0msl1dt2) can0 message slot 1 data 4 (c0msl1dt4) h'0080 1118 h'0080 111a h'0080 111e h'0080 1120 h'0080 1122 h'0080 1126 h'0080 1128 h'0080 112e h'0080 112c h'0080 1124 h'0080 112a can0 message slot 2 data 6 (c0msl2dt6) can0 message slot 2 time stamp (c0msl2tsp) can0 message slot 2 data 7 (c0msl2dt7) h'0080 111c can0 message slot 2 data 4 (c0msl2dt4) can0 message slot 2 data 2 (c0msl2dt2) can0 message slot 2 data 0 (c0msl2dt0) can0 message slot 2 extended id2 (c0msl2eid2) can0 message slot 2 extended id0 (c0msl2eid0) can0 message slot 2 standard id0 (c0msl2sid0) can0 message slot 1 time stamp (c0msl1tsp) can0 message slot 1 data 6 (c0msl1dt6) can0 message slot 2 data 5 (c0msl2dt5) can0 message slot 2 data 3 (c0msl2dt3) can0 message slot 2 data 1 (c0msl2dt1) can0 message slot 2 data length register (c0msl2dlc) can0 message slot 2 extended id1 (c0msl2eid1) can0 message slot 2 standard id1 (c0msl2sid1) can0 message slot 1 data 7 (c0msl1dt7) h'0080 1130 h'0080 1132 h'0080 1136 h'0080 1138 h'0080 113e h'0080 113c h'0080 1134 h'0080 113a can0 message slot 3 data 6 (c0msl3dt6) can0 message slot 3 time stamp (c0msl3tsp) can0 message slot 3 data 7 (c0msl3dt7) can0 message slot 3 data 4 (c0msl3dt4) can0 message slot 3 data 2 (c0msl3dt2) can0 message slot 3 data 0 (c0msl3dt0) can0 message slot 3 extended id2 (c0msl3eid2) can0 message slot 3 extended id0 (c0msl3eid0) can0 message slot 3 standard id0 (c0msl3sid0) can0 message slot 3 data 5 (c0msl3dt5) can0 message slot 3 data 3 (c0msl3dt3) can0 message slot 3 data 1 (c0msl3dt1) can0 message slot 3 data length register (c0msl3dlc) can0 message slot 3 extended id1 (c0msl3eid1) can0 message slot 3 standard id1 (c0msl3sid1) h'0080 1140 h'0080 1142 h'0080 1146 h'0080 1148 h'0080 114e h'0080 114c h'0080 1144 h'0080 114a can0 message slot 4 data 6 (c0msl4dt6) can0 message slot 4 time stamp (c0msl4tsp) can0 message slot 4 data 7 (c0msl4dt7) can0 message slot 4 data 4 (c0msl4dt4) can0 message slot 4 data 2 (c0msl4dt2) can0 message slot 4 data 0 (c0msl4dt0) can0 message slot 4 extended id2 (c0msl4eid2) can0 message slot 4 extended id0 (c0msl4eid0) can0 message slot 4 standard id0 (c0msl4sid0) can0 message slot 4 data 5 (c0msl4dt5) can0 message slot 4 data 3 (c0msl4dt3) can0 message slot 4 data 1 (c0msl4dt1) can0 message slot 4 data length register (c0msl4dlc) can0 message slot 4 extended id1 (c0msl4eid1) can0 message slot 4 standard id1 (c0msl4sid1) h'0080 1150 h'0080 1152 can0 message slot 5 extended id0 (c0msl5eid0) can0 message slot 5 standard id0 (c0msl5sid0) can0 message slot 5 extended id1 (c0msl5eid1) can0 message slot 5 standard id1 (c0msl5sid1) h'0080 1100 can0 message slot 0 standard id1 (c0msl0sid1) can0 message slot 0 standard id0 (c0msl0sid0) blank addresses are reserved areas. +0 address +1 address address
3 3-26 ver.0.10 address space 3.4 internal rom/sfr area figure 3.4.18 register mapping of the sfr area (15) d0 d7 d8 d15 h'0080 1156 h'0080 1158 h'0080 115e h'0080 115c h'0080 1154 h'0080 115a h'0080 1160 h'0080 1162 h'0080 1166 h'0080 1168 h'0080 116e h'0080 116c h'0080 1164 h'0080 116a h'0080 1170 h'0080 1172 h'0080 1176 h'0080 1174 can0 message slot 5 data 6 (c0msl5dt6) can0 message slot 5 time stamp (c0msl5tsp) can0 message slot 5 data 7 (c0msl5dt7) can0 message slot 5 data 4 (c0msl5dt4) can0 message slot 5 data 2 (c0msl5dt2) can0 message slot 5 data 0 (c0msl5dt0) can0 message slot 5 extended id2 (c0msl5eid2) can0 message slot 5 data 5 (c0msl5dt5) can0 message slot 5 data 3 (c0msl5dt3) can0 message slot 5 data 1 (c0msl5dt1) can0 message slot 5 data length register (c0msl5dlc) can0 message slot 6 data 6 (c0msl6dt6) can0 message slot 6 time stamp (c0msl6tsp) can0 message slot 6 data 7 (c0msl6dt7) can0 message slot 6 data 4 (c0msl6dt4) can0 message slot 6 data 2 (c0msl6dt2) can0 message slot 6 data 0 (c0msl6dt0) can0 message slot 6 extended id2 (c0msl6eid2) can0 message slot 6 extended id0 (c0msl6eid0) can0 message slot 6 standard id0 (c0msl6sid0) can0 message slot 6 data 5 (c0msl6dt5) can0 message slot 6 data 3 (c0msl6dt3) can0 message slot 6 data 1 (c0msl6dt1) can0 message slot 6 data length register (c0msl6dlc) can0 message slot 6 extended id1 (c0msl6eid1) can0 message slot 6 standard id1 (c0msl6sid1) can0 message slot 7 data 0 (c0msl7dt0) can0 message slot 7 extended id2 (c0msl7eid2) can0 message slot 7 extended id0 (c0msl7eid0) can0 message slot 7 standard id0 (c0msl7sid0) can0 message slot 7 data 1 (c0msl7dt1) can0 message slot 7 data length register (c0msl7dlc) can0 message slot 7 extended id1 (c0msl7eid1) can0 message slot 7 standard id1 (c0msl7sid1) h'0080 117a h'0080 117c h'0080 117e h'0080 1182 h'0080 1184 h'0080 118a h'0080 1188 h'0080 1180 h'0080 1186 h'0080 1178 h'0080 118c h'0080 118e h'0080 1192 h'0080 1194 h'0080 119a h'0080 1198 h'0080 1190 h'0080 1196 h'0080 119c h'0080 119e can0 message slot 8 data 6 (c0msl8dt6) can0 message slot 8 time stamp (c0msl8tsp) can0 message slot 8 data 7 (c0msl8dt7) can0 message slot 8 data 4 (c0msl8dt4) can0 message slot 8 data 2 (c0msl8dt2) can0 message slot 8 data 0 (c0msl8dt0) can0 message slot 8 extended id2 (c0msl8eid2) can0 message slot 8 extended id0 (c0msl8eid0) can0 message slot 8 standard id0 (c0msl8sid0) can0 message slot 8 data 5 (c0msl8dt5) can0 message slot 8 data 3 (c0msl8dt3) can0 message slot 8 data 1 (c0msl8dt1) can0 message slot 8 data length register (c0msl8dlc) can0 message slot 8 extended id1 (c0msl8 eid1) can0 message slot 8 standard id1 (c0msl8sid1) can0 message slot 7 data 6 (c0msl7dt6) can0 message slot 7 time stamp (c0msl7tsp) can0 message slot 7 data 7 (c0msl7dt7) can0 message slot 7 data 4 (c0msl7dt4) can0 message slot 7 data 2 (c0msl7dt2) can0 message slot 7 data 5 (c0msl7dt5) can0 message slot 7 data 3 (c0msl7dt3) can0 message slot 9 data 6 (c0msl9dt6) can0 message slot 9 time stamp (c0msl9tsp) can0 message slot 9 data 7 (c0msl9dt7) can0 message slot 9 data 4 (c0msl9dt4) can0 message slot 9 data 2 (c0msl9dt2) can0 message slot 9 data 0 (c0msl9dt0) can0 message slot 9 extended id2 (c0msl9eid2) can0 message slot 9 extended id0 (c0msl9eid0) can0 message slot 9 standard id0 (c0msl9sid0) can0 message slot 9 data 5 (c0msl9dt5) can0 message slot 9 data 3 (c0msl9dt3) can0 message slot 9 data 1 (c0msl9dt1) can0 message slot 9 data length register (c0msl9dlc) can0 message slot 9 extended id1 (c0msl9eid1) can0 message slot 9 standard id1 (c0msl9sid1) h'0080 11a2 h'0080 11a4 h'0080 11a0 can0 message slot 10 extended id2 (c0msl10eid2) can0 message slot 10 extended id0 (c0msl10eid0) can0 message slot 10 standard id0 (c0msl10sid0) can0 message slot 10 data length register (c0msl10dlc) can0 message slot 10 extended id1 (c0msl10eid1) can0 message slot 10 standard id1 (c0msl10sid1) h'0080 11a6 can0 message slot 10 data 0 (c0msl10dt0) can0 message slot 10 data 1 (c0msl10dt1) blank addresses are reserved areas. +0 address +1 address address
3 3-27 ver.0.10 figure 3.4.19 register mapping of the sfr area (16) address space 3.4 internal rom/sfr area d0 d7 d8 d15 h'0080 11aa h'0080 11a8 h'0080 11ac h'0080 11ae h'0080 11b2 h'0080 11bc h'0080 11ba h'0080 11b8 h'0080 11b0 h'0080 11b6 h'0080 11be h'0080 11c2 h'0080 11c4 h'0080 11ca h'0080 11c8 h'0080 11c0 h'0080 11c6 h'0080 11ce h'0080 11d2 h'0080 11d0 can0 message slot 10 data 6 (c0msl10dt6) can0 message slot 10 time stamp (c0msl10tsp) can0 message slot 10 data 7 (c0msl10dt7) can0 message slot 10 data 4 (c0msl10dt4) can0 message slot 10 data 2 (c0msl10dt2) can0 message slot 10 data 5 (c0msl10dt5) can0 message slot 10 data 3 (c0msl10dt3) can0 message slot 11 data 6 (c0msl11dt6) can0 message slot 11 time stamp (c0msl11tsp) can0 message slot 11 data 7 (c0msl11dt7) can0 message slot 11 data 4 (c0msl11dt4) can0 message slot 11 data 2 (c0msl11dt2) can0 message slot 11 data 0 (c0msl11dt0) can0 message slot 11 extended id2 (c0msl11eid2) can0 message slot 11 extended id0 (c0msl11eid0) can0 message slot 11 standard id0 (c0msl11sid0) can0 message slot 11 data 5 (c0msl11dt5) can0 message slot 11 data 3 (c0msl11dt3) can0 message slot 11 data 1 (c0msl11dt1) can0 message slot 11 data length register (c0msl11dlc) can0 message slot 11 extended id1 (c0msl11eid1) can0 message slot 11 standard id1 (c0msl11sid1) can0 message slot 12 data 6 (c0msl12dt6) can0 message slot 12 time stamp (c0msl12tsp) can0 message slot 12 data 7 (c0msl12dt7) can0 message slot 12 data 4 (c0msl12dt4) can0 message slot 12 data 2 (c0msl12dt2) can0 message slot 12 data 0 (c0msl12dt0) can0 message slot 12 extended id2 (c0msl12eid2) can0 message slot 12 extended id0 (c0msl12eid0) can0 message slot 12 standard id0 (c0msl12sid0) can0 message slot 12 data 5 (c0msl12dt5) can0 message slot 12 data 3 (c0msl12dt3) can0 message slot 12 data 1 (c0msl12dt1) can0 message slot 12 data length register (c0msl12dlc) can0 message slot 12 extended id1 (c0msl12eid1) can0 message slot 12 standard id1 (c0msl12sid1) can0 message slot 13 extended id0 (c0msl13eid0) can0 message slot 13 standard id0 (c0msl13sid0) can0 message slot 13 extended id1 (c0msl13eid1) can0 message slot 13 standard id1 (c0msl13sid1) h'0080 11d6 h'0080 11d8 h'0080 11da h'0080 11de h'0080 11e0 h'0080 11e6 h'0080 11e4 h'0080 11dc h'0080 11e2 h'0080 11d4 h'0080 11e8 h'0080 11ea h'0080 11ee h'0080 11f0 h'0080 11f6 h'0080 11f4 h'0080 11ec h'0080 11f2 h'0080 11f8 h'0080 11fa h'0080 11fe h'0080 3ffe h'0080 11fc can0 message slot 14 data 6 (c0msl14dt6) can0 message slot 14 time stamp (c0msl14tsp) can0 message slot 14 data 7 (c0msl14dt7) can0 message slot 14 data 4 (c0msl14dt4) can0 message slot 14 data 2 (c0msl14dt2) can0 message slot 14 data 0 (c0msl14dt0) can0 message slot 14 extended id2 (c0msl14eid2) can0 message slot 14 extended id0 (c0msl14eid0) can0 message slot 14 standard id0 (c0msl14sid0) can0 message slot 14 data 5 (c0msl14dt5) can0 message slot 14 data 3 (c0msl14dt3) can0 message slot 14 data 1 (c0msl14dt1) can0 message slot 14 data length register (c0msl14dlc) can0 message slot 14 extended id1 (c0msl14eid1) can0 message slot 14 standard id1 (c0msl14sid1) can0 message slot 13 data 6 (c0msl13dt6) can0 message slot 13 time stamp (c0msl13tsp) can0 message slot 13 data 7 (c0msl13dt7) can0 message slot 13 data 4 (c0msl13dt4) can0 message slot 13 data 2 (c0msl13dt2) can0 message slot 13 data 0 (c0msl13dt0) can0 message slot 13 extended id2 (c0msl13eid2) can0 message slot 13 data 5 (c0msl13dt5) can0 message slot 13 data 3 (c0msl13dt3) can0 message slot 13 data 1 (c0msl13dt1) can0 message slot 15 data 6 (c0msl15dt6) can0 message slot 15 time stamp (c0msl11tsp) can0 message slot 15 data 7 (c0msl15dt7) can0 message slot 15 data 4 (c0msl15dt4) can0 message slot 15 data 2 (c0msl15dt2) can0 message slot 15 data 0 (c0msl15dt0) can0 message slot 15 extended id2 (c0msl15eid2) can0 message slot 15 extended id0 (c0msl15eid0) can0 message slot 15 standard id0 (c0msl15sid0) can0 message slot 15 data 5 (c0msl15dt5) can0 message slot 15 data 3 (c0msl15dt3) can0 message slot 15 data 1 (c0msl15dt1) can0 message slot 15 data length register (c0msl15dlc) can0 message slot 15 extended id1 (c0msl15eid1) can0 message slot 15 standard id1 (c0msl15sid1) can0 message slot 13 data length register (c0msl13dlc) h'0080 11cc h'0080 11b4 blank addresses are reserved areas. +0 address +1 address address ~ ~ ~ ~
3 3-28 ver.0.10 address space 3.5 eit vector entry 3.5 eit vector entry the eit vector entry is located at the beginning of the internal rom/extended external areas. instructions for branching to the start addresses of respective eit event handlers are written here. note that it is branch instructions and not the jump addresses that are written here. for details, refer to chapter 4, "eit." figure 3.5.1 eit vector entry note: when flash entry bit = 1 (i.e., flash enable mode), the ei vector entry is at h'0080 4000. h'0000 0040 trap0 trap1 trap2 trap3 trap4 trap5 trap6 trap7 trap8 trap9 trap10 trap11 trap12 trap13 trap14 trap15 ae (address exception) ei (external interrupt) (note) h'0000 0044 h'0000 0048 h'0000 004c h'0000 0050 h'0000 0054 h'0000 0058 h'0000 005c h'0000 0060 h'0000 0064 h'0000 0068 h'0000 006c h'0000 0070 h'0000 0074 h'0000 0078 h'0000 007c h'0000 0080 ri (reset interrupt) sbi (system break interrupt) rie (reserved instruction exception) h'0000 0030 h'0000 0020 h'0000 0010 h'0000 0000 031 h'0000 0034 h'0000 0038 h'0000 003c h'0000 0024 h'0000 0028 h'0000 002c h'0000 0004 h'0000 0008 h'0000 000c h'0000 0014 h'0000 0018 h'0000 001c ~ ~
3 3-29 ver.0.10 3.6 icu vector table the icu vector table is used by the internal interrupt controller. the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral i/os are set at the ad- dresses shown below. for details, refer to chapter 5, "interrupt controller." the 32170's icu vector table is shown in figures 3.6.1 and 3.6.2. address space 3.6 icu vector table figure 3.6.1 icu vector table of the 32170 (1/2) h'0000 0094 address d0 d7 +0 address +1 address d8 d15 h'0000 0096 mjt input interrupt 4 handler start address (a0-a15) mjt input interrupt 4 handler start address (a16-a31) h'0000 0098 h'0000 009a h'0000 009c h'0000 009e h'0000 00a0 h'0000 00a2 h'0000 00a4 h'0000 00a6 h'0000 00a8 h'0000 00aa h'0000 00ac h'0000 00ae h'0000 00b0 h'0000 00b2 h'0000 00b4 h'0000 00b6 h'0000 00b8 h'0000 00ba h'0000 00bc h'0000 00be h'0000 00c0 h'0000 00c2 h'0000 00c4 h'0000 00c6 mjt output interrupt 7 handler start address (a0-a15) mjt output interrupt 7 handler start address (a16-a31) mjt input interrupt 3 handler start address (a0-a15) mjt input interrupt 3 handler start address (a16-a31) mjt input interrupt 2 handler start address (a0-a15) mjt input interrupt 2 handler start address (a16-a31) mjt input interrupt 1 handler start address (a0-a15) mjt input interrupt 1 handler start address (a16-a31) mjt input interrupt 0 handler start address (a0-a15) mjt input interrupt 0 handler start address (a16-a31) mjt output interrupt 6 handler start address (a0-a15) mjt output interrupt 6 handler start address (a16-a31) mjt output interrupt 5 handler start address (a0-a15) mjt output interrupt 5 handler start address (a16-a31) mjt output interrupt 4 handler start address (a0-a15) mjt output interrupt 4 handler start address (a16-a31) mjt output interrupt 3 handler start address (a0-a15) mjt output interrupt 3 handler start address (a16-a31) mjt output interrupt 2 handler start address (a0-a15) mjt output interrupt 2 handler start address (a16-a31) mjt output interrupt 1 handler start address (a0-a15) mjt output interrupt 1 handler start address (a16-a31) mjt output interrupt 0 handler start address (a0-a15) mjt output interrupt 0 handler start address (a16-a31) ~ ~
3 3-30 ver.0.10 address space 3.6 icu vector table figure 3.6.2 icu vector table of the 32170 (2/2) h'0000 00c8 address d0 d7 +0 address +1 address d8 d15 h'0000 00ca dma0-4 interrupt handler start address (a0-a15) dma0-4 interrupt handler start address (a16-a31) h'0000 00cc h'0000 00ce h'0000 00d0 h'0000 00d2 h'0000 00d4 h'0000 00d6 h'0000 00d8 h'0000 00da h'0000 00dc h'0000 00de sio1 receive interrupt handler start address (a0-a15) sio1 receive interrupt handler start address (a16-a31) sio1 transmit interrupt handler start address (a0-a15) sio1 transmit interrupt handler start address (a16-a31) a-d0 conversion interrupt handler start address (a0-a15) a-d0 conversion interrupt handler start address (a16-a31) h'0000 00e0 h'0000 00e2 h'0000 00e4 h'0000 00e6 h'0000 00e8 h'0000 00ea h'0000 00ec h'0000 00ee tid0 output interrupt handler start address (a0-a15) tid0 output transmit interrupt handler start address (a16-a31) tod0 output interrupt handler start address (a0-a15) tod0 output interrupt handler start address (a16-a31) dma5-9 interrupt handler start address (a0-a15) dma5-9 interrupt handler start address (a16-a31) sio2,3 transmit/receive interrupt handler start address (a0-a15) sio2,3 transmit/receive interrupt handler start address (a16-a31) h'0000 00f0 h'0000 00f2 rtd interrupt handler start address (a0-a15) rtd interrupt handler start address (a16-a31) h'0000 00f4 h'0000 00f6 tid1 output interrupt handler start address (a0-a15) tid1 output interrupt handler start address (a16-a31) h'0000 00f8 h'0000 00fa tod1+tom0 output interrupt handler start address (a0-a15) tod1+tom0 output interrupt handler start address (a16-a31) h'0000 00fc h'0000 00fe sio4,5 transmit/receive interrupt handler start address (a0-a15) sio4,5 transmit/receive interrupt handler start address (a16-a31) h'0000 0100 h'0000 0102 a-d1 conversion interrupt handler start address (a0-a15) a-d1 conversion interrupt handler start address (a16-a31) h'0000 0104 h'0000 0106 tid2 output interrupt handler start address (a0-a15) tid2 output interrupt handler start address (a16-a31) h'0000 0108 h'0000 010a tml1 input interrupt handler start address (a0-a15) tml1 input interrupt handler start address (a16-a31) h'0000 010c h'0000 010e can0 transmit/receive & error interrupt handler start address (a0-a15) can0 transmit/receive & error interrupt handler start address (a16-a31) sio0 receive interrupt handler start address (a0-a15) sio0 receive interrupt handler start address (a16-a31) sio0 transmit interrupt handler start address (a0-a15) sio0 transmit interrupt handler start address (a16-a31)
3 3-31 ver.0.10 address space 3.7 notes on address space 3.7 note about address space ? virtual flash emulation function the 32170 has a special function, called the "virtual flash emulation function," which allows the internal ram to be mapped in blocks of 8 kbytes from the beginning (up to four blocks for the m32170f6, up to three blocks for the m32170f4 and m32170f3) into internal flash memory areas divided in 8 kbytes (l banks). similarly, this function allows the internal ram to be mapped in blocks of 4 kbytes, for the m32170f6 (up to two blocks) starting from the ram address h'0080 c000, for the m32170f4 and m32170f3 (up to two blocks) starting from the ram address h'0080 a000 into internal flash memory areas divided in 4 kbytes (s banks). for details about this function, refer to section 6.7, "pseudo-flash emulation function."
3 3-32 ver.0.10 address space 3.7 notes on address space j this is a blank page. j
chapter 4 chapter 4 eit 4.1 outline of eit 4.2 eit event 4.3 eit processing procedure 4.4 eit processing mechanism 4.5 acceptance of eit events 4.6 saving and restoring the pc and psw 4.7 eit vector entry 4.8 exception processing 4.9 interrupt processing 4.10 trap processing 4.11 eit priority levels 4.12 example of eit processing
4 4-2 ver.0.10 eit 4.1 outline of eit 4.1 outline of eit if some event occurs when the cpu is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. events like this one are referred to by a generic name as eit (exception, interrupt, and trap). (1) exception this is an event related to the context being executed. it is generated by an error or violation during instruction execution. in the m32r/e, this type of event includes address exception (ae) and reserved instruction exception (rie). (2) interrupt this is an event generated irrespective of the context being executed. it is generated in hardware by a signal from an external source. in the m32r/e, this type of event includes external interrupt (ei), system break interrupt (sbi), and reset interrupt (ri). (3) trap this refers to a software interrupt generated by executing a trap instruction. this type of event is intentionally generated in a program as in the os's system call by the programmer. eit exception reserved instruction exception (rie) address exception (ae) interrupt reset interrupt (ri) system break interrupt (sbi) external interrupt (ei) trap trap figure 4.1.1 classification of eits
4 4-3 ver.0.10 eit 4.2 eit event 4.2 eit event 4.2.1 exception (1) reserved instruction exception (rie) reserved instruction exception (rie) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) address exception (ae) address exception (ae) is generated when an attempt is made to access a misaligned address in load or store instructions. 4.2.2 interrupt (1) reset interrupt (ri) ____________ reset interrupt (ri) is always accepted by entering the reset signal. the reset interrupt is assigned the highest priority. (2) system break interrupt (sbi) system break interrupt (sbi) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. this interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) external interrupt (ei) external interrupt (ei) is requested from internal peripheral i/os managed by the interrupt controller. the 32170's internal interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. 4.2.3 trap traps are software interrupts which are generated by executing the trap instruction. sixteen distinct vector addresses are provided corresponding to trap instruction operands 0-15.
4 4-4 ver.0.10 4.3 eit processing procedure eit processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (eit handlers). the procedure for processing eits when accepted, except for a rest interrupt, is shown below. figure 4.3.1 outline of eit processing procedure instruction a instruction b instruction c pc bpc psw (b)psw eit vector entry eit handlers except for sbi rte instruc- tion instruction c instruction d program suspended eit request accepted instruction processing- canceled type (rie, ae) instruction processing -completed type (ei, trap) program execution restarted eit request generated hardware preprocessing bpc, (b)psw, and general-purpose registers saved to stack branch instruc -tion general-purpose registers, (b)psw, and bpc restored from stack sbi (system break interrupt processing) hardware postprocessing (sbi) program terminated or system is reset user-created eit handler (b)psw psw bpc pc processing by handler note: (b)psw denotes the bpsw field of the psw register. eit 4.3 eit processing procedure
4 4-5 ver.0.10 when an eit is accepted, the m32r/e saves the pc and psw (as will be described later) and branches to the eit vector. the eit vector has an entry address assigned for each eit. this is where the bra (branch) instruction (note that these are not branch address) for the eit handler is written. in the m32r/e's hardware preprocessing, only the contents of the pc and psw registers are transferred to the backup registers (bpc register and the bpsw field of the psw register), and no other operations are performed. therefore, please make sure the bpc register, the psw register (including the bpsw field), and the general-purpose registers to be used in the eit handler are saved to the stack by the eit handler you write. (remember that these registers must be saved to the stack in a program by the user.) when processing by the eit handler is completed, restore the saved registers from the stack and finally execute the "rte" instruction. control is thereby returned from eit processing to the program that was being executed when the eit occurred. (this does not apply to the system break interrupt, however.) in the m32r/e's hardware postprocessing, the contents of the backup registers (bpc register and the bpsw field of the psw register) are moved back to the pc and psw registers. eit 4.3 eit processing procedure
4 4-6 ver.0.10 4.4 eit processing mechanism the m32r/e's eit processing mechanism consists of the m32r cpu core and the interrupt controller for internal peripheral i/os. it also has the backup registers for the pc and psw (bpc register and the bpsw field of the psw register). the m32r/e's internal eit processing mechanism is shown below. figure 4.4.1 the m32r/e's eit processing mechanism interrupt controller (icu) sbi ei internal peripheral i/o reset ri ae, rie, trap ie flag (psw) m32r cpu core sbi low high priority sbi ei ri m32r/e psw register psw bpsw bpc register pc register eit 4.4 eit processing mechanism
4 4-7 ver.0.10 4.5 acceptance of eit event when an eit event occurs, the m32r/e suspends the program it has hitherto been executing and branches to eit processing by the relevant handler. conditions under which each eit event occurs and the timing at which they are accepted are shown below. table 4.5.1 acceptance of eit events eit event type of processing acceptance timing values set in bpc register reserved instruction instruction processing - during instruction pc value of the instruction exception (rie) canceled type execution which generated rie address exception (ae) instruction processing - during instruction pc value of the instruction canceled type execution which generated ae reset interrupt (ri) instruction processing- each machine cycle indeterminate value aborted type system break instruction processing- break in instructions pc value of the next instruction interrupt (sbi) completed type (only word boundaries) external interrupt (ei) instruction processing- break in instructions pc value of the next instruction completed type (only word boundaries) trap (trap) instruction processing- break in instructions pc value of trap completed type instruction + 4 eit 4.5 acceptance of eit events
4 4-8 ver.0.10 4.6 saving and restoring the pc and psw the following describes operation of the m32r at the time when it accepts an eit and when it executes the "rte" instruction. (1) hardware preprocessing when an eit is accepted save the sm, ie, and c bits of the psw register bsm ? sm bie ? ie bc ? c update the sm, ie, and c bits of the psw register sm ? remains unchanged (rie, ae, trap) or set to 0 (sbi, ei, ri) ie ? set to 0 c ? set to 0 a save the pc register bpc ? pc ? set the vector address in the pc register branches to the eit vector and executes the branch instruction ("bra" instruction) written in it, thereby transferring control to the user-created eit handler. (2) hardware postprocessing when the "rte" instruction is executed ? restore the sm, ie, and c bits of the psw register from their backup bits. sm ? bsm ie ? bie c ? bc restore the value of the pc register from the bpc register pc ? bpc note: the value of the bpc register and those of the bsm, bie, and bc bits of the psw register after execution of the "rte" instruction are indeterminate. eit 4.6 saving and restoring the pc and psw
4 4-9 ver.0.10 figure 4.6.1 saving and restoring the pc and psw a a a a psw bpc pc when eit is accepted when "rte" instruction is executed 2 3 4 1 2 1 aaaa aaaa aaaa aaaa 1 2 save sm, ie, and c bits bsm bie bc sm ie c update sm, ie, and c bits sm ie c unchanged/0 0 0 3 4 save pc bpc pc set vector address in pc pc vector address restore pc value from bpc the value of bpc after execution of the "rte" instruction is indeterminate. 2 1 restore bsm, bie, and bc bits from backup bits sm ie c the values of bsm, bie, and bc bits after execution of the "rte" instruction are indeterminate. bsm bie bc 16 17 23 24 25 31(lsb) 15 8 7 0(msb) sm ie c bc bsm bie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psw bpsw field psw field eit 4.6 saving and restoring the pc and psw
4 4-10 ver.0.10 4.7 eit vector entry the eit vector entry is located in the user space starting from address h'0000 0000. the table below lists the eit vector entry. table 4.7.1 eit vector entry note 1: during boot mode, this vector address is moved to the beginning of the boot rom (address h'8000 0000). for details, refer to section 6.5, "programming of internal flash memory." note 2: during flash e/w enable mode, this vector address is moved to the beginning of the internal ram (address h'0080 4000). for details, refer to section 6.5, "programming of internal flash memory." name abbreviation vector address sm ie bpc reset interrupt ri h'0000 0000 (note 1) 0 0 indeterminate system break interrupt sbi h'0000 0010 0 0 pc of the next instruction reserved instruction rie h'0000 0020 indeterminate 0 pc of the instruction that exception generated eit address exception ae h'0000 0030 indeterminate 0 pc of the instruction that generated rie trap trap0 h'0000 0040 indeterminate 0 pc of trap instruction + 4 trap1 h'0000 0044 indeterminate 0 pc of trap instruction + 4 trap2 h'0000 0048 indeterminate 0 pc of trap instruction + 4 trap3 h'0000 004c indeterminate 0 pc of trap instruction + 4 trap4 h'0000 0050 indeterminate 0 pc of trap instruction + 4 trap5 h'0000 0054 indeterminate 0 pc of trap instruction + 4 trap6 h'0000 0058 indeterminate 0 pc of trap instruction + 4 trap7 h'0000 005c indeterminate 0 pc of trap instruction + 4 trap8 h'0000 0060 indeterminate 0 pc of trap instruction + 4 trap9 h'0000 0064 indeterminate 0 pc of trap instruction + 4 trap10 h'0000 0068 indeterminate 0 pc of trap instruction + 4 trap11 h'0000 006c indeterminate 0 pc of trap instruction + 4 trap12 h'0000 0070 indeterminate 0 pc of trap instruction + 4 trap13 h'0000 0074 indeterminate 0 pc of trap instruction + 4 trap14 h'0000 0078 indeterminate 0 pc of trap instruction + 4 trap15 h'0000 007c indeterminate 0 pc of trap instruction + 4 external interrupt ei h'0000 0080 (note 2) 0 0 pc of the next instruction eit 4.7 eit vector entry
4 4-11 ver.0.10 4.8 exception processing 4.8.1 reserved instruction exception (rie) [occurrence conditions] reserved instruction exception (rie) is generated when execution of a reserved instruction (unimplemented instruction) is detected. instruction check is performed on the op-code part of the instruction. when a reserved instruction exception occurs, the instruction which generated it is not executed. if an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [eit processing] (1) saving sm, ie, and c bits the sm, ie, and c bits of the psw register are saved to their backup bits C the bsm, bie, and bc bits. bsm ? sm bie ? ie bc ? c (2) updating sm, ie, and c bits the sm, ie, and c bits of the psw register are updated as shown below. sm ? unchanged bie ? 0 bc ? 0 (3) saving pc the pc value of the instruction that generated the reserved instruction exception is set in the bpc register. for example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the bpc register. similarly, if the instruction is at address 6, the value 6 is set in the bpc register. in this case, the value of the bpc register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the "rte" instruction returns after completion of processing by the eit handler is address 4. (this is because the two low-order bits are cleared to "00" when returning to the pc.) eit 4.8 exception processing
4 4-12 ver.0.10 figure 4.8.1 example of a return address for reserved instruction exception (rie) (4) branching to the eit vector entry control branches to the address h'0000 0020 in the user space. this is the last operation performed in hardware preprocessing by the m32r/e. (5) jumping from the eit vector entry to the user-created handler the m32r/e executes the "bra" instruction written at address h'0000 0020 of the eit vector entry by the user to jump to the start address of the user-created handler. at the beginning of the eit handler you created, first save the bpc and psw registers and the necessary general-purpose registers to the stack. (6) returning from the eit handler at the end of the eit handler, restore the general-purpose registers and the bpc and psw registers from the stack and then execute the "rte" instruction. as you execute the "rte" instruction, hardware postprocessing is automatically performed by the m32r/e. h'00 address rie occurred h'04 h'08 h'0c +0 +1 +2 +3 h'00 address rie occurred h'04 h'08 h'0c +0 +1 +2 +3 return address return address bpc h'06 bpc h'04 ~ ~ ~ ~ ~ ~ ~ ~ eit 4.8 exception processing
4 4-13 ver.0.10 4.8.2 address exception (ae) [occurrence conditions] address exception (ae) is generated when an attempt is made to access a misaligned address in load or store instructions. the following lists the combination of instructions and accessed addresses that may cause address exceptions to occur: ? when the ldh, lduh, or sth instruction accesssed an address whose two low-order bits are "01" or "11" ? when the ld, st, lock, or unlock instruction accessed an address whose two low-order bits are "01," "10," or "11" when an address exception occurs, memory access by the instruction that generated the exception is not performed. if an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [eit processing] (1) saving sm, ie, and c bits the sm, ie, and c bits of the psw register are saved to their backup bits C the bsm, bie, and bc bits. bsm ? sm bie ? ie bc ? c (2) updating sm, ie, and c bits the sm, ie, and c bits of the psw register are updated as shown below. sm ? unchanged ie ? 0 c ? 0 (3) saving pc the pc value of the instruction that generated the address exception is set in the bpc register. for example, if the instruction that generated the address exception is at address 4, the value 4 is set in the bpc register. similarly, if the instruction is at address 6, the value 6 is set in the bpc register. in this case, the value of the bpc register bit 30 indicates whether the instruction that generated the address exception resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the "rte" instruction returns after completion of processing by the eit handler is address 4. (this is because the two low-order bits are cleared to "00" when returning to the pc.) eit 4.8 exception processing
4 4-14 ver.0.10 figure 4.8.2 example of a return address for address exception (ae) (4) branching to the eit vector entry control branches to the address h'0000 0030 in the user space. this is the last operation performed in hardware preprocessing by the m32r/e. (5) jumping from the eit vector entry to the user-created handler the m32r/e executes the "bra" instruction written at address h'0000 0030 of the eit vector entry by the user to jump to the start address of the user-created handler. at the beginning of the eit handler you created, first save the bpc and psw registers and the necessary general-purpose registers to the stack. (6) returning from the eit handler at the end of the eit handler, restore the general-purpose registers and the bpc and psw registers from the stack and then execute the "rte" instruction. as you execute the "rte" instruction, hardware postprocessing is automatically performed by the m32r/e. h'00 address ae occurred h'04 h'08 h'0c +0 +1 +2 +3 h'00 address ae occurred h'04 h'08 h'0c +0 +1 +2 +3 return address return address bpc h'06 bpc h'04 ~ ~ ~ ~ ~ ~ ~ ~ eit 4.8 exception processing
4 4-15 ver.0.10 4.9 interrupt processing 4.9.1 reset interrupt (ri) [occurrence conditions] ____________ reset interrupt (ri) is unconditionally accepted in any machine cycle by pulling the reset input signal low. the reset interrupt is assigned the highest priority among all eits. [eit processing] (1) initializing sm, ie, and c bits the sm, ie, and c bits of the psw register are initialized in the manner shown below. for the reset interrupt, the values of bsm, bie, and bc bits are indeterminate. sm ? 0 ie ? 0 c ? 0 (2) branching to the eit vector entry control branches to the address h'0000 0000 in the user space. however, when operating in boot mode, control goes to the beginning of the boot rom (address h'8000 0000). for details, refer to section 6.5, "programming of internal flash memory." (3) jumping from the eit vector entry to the user program the m32r/e executes the instruction written at address h'0000 0000 of the eit vector entry by the user. in the reset vector entry, be sure to initialize the psw and spi registers before jumping to the start address of the program you created. eit 4.9 interrupt processing
4 4-16 ver.0.10 4.9.2 system break interrupt (sbi) system break interrupt (sbi) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. the system break interrupt cannot be masked by the psw register ie bit. therefore, the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected. also, this interrupt must be used on condition that after processing by the sbi handler, control will not return to the program that was being executed when the system break interrupt occurred. [occurrence conditions] _______ a system break interrupt is accepted by a falling edge on sbi input pin. (the system break interrupt cannot be masked by the psw register ie bit.) in no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (for 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) figure 4.9.1 timing at which system break interrupt (sbi) is accepted 16-bit instruction order in which instructions are executed address 1000 interrupt may be accepted interrupt cannot be accepted address 1002 address 1004 address 1008 16-bit instruction 32-bit instruction interrupt may be accepted interrupt may be accepted eit 4.9 interrupt processing
4 4-17 ver.0.10 [eit processing] (1) saving sm, ie, and c bits the sm, ie, and c bits of the psw register are saved to their backup bits-the bsm, bie, and bc bits. bsm ? sm bie ? ie bc ? c (2) updating sm, ie, and c bits the sm, ie, and c bits of the psw register are updated as shown below. sm ? 0 ie ? 0 c ? 0 (3) saving pc the content (always word boundary) of the pc register is saved to the bpc register. (4) branching to the eit vector entry control branches to the address h'0000 0010 in the user space. this is the last operation performed in hardware preprocessing by the m32r/e. (5) jumping from the eit vector entry to the user-created handler the m32r/e executes the "bra" instruction written at address h'0000 0010 of the eit vector entry by the user to jump to the start address of the user-created handler. the system break interrupt can only be used when some fatal event has occurred to the system. also, this interrupt must be used on condition that after processing by the sbi handler, control will not return to the program that was being executed when the system break interrupt occurred. eit 4.9 interrupt processing
4 4-18 ver.0.10 4.9.3 external interrupt (ei) an external interrupt is generated upon an interrupt request which is output by the 32170's internal interrupt controller. the interrupt controller manages interrupt requests by assigning each one of seven priority levels. for details, refer to chapter 5, "interrupt controller." for details about the interrupt sources, refer to each section in which the relevant internal peripheral i/o is described. [occurrence conditions] external interrupts are managed based on interrupt requests from each internal peripheral i/o by the 32170's internal interrupt controller. these interrupt requests are notified to the m32r cpu by the interrupt controller. the m32r/e checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the psw register ie flag = 1, accepts it as an external interrupt. in no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (for 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) figure 4.9.2 timing at which external interrupt (ei) is accepted 16-bit instruction order in which instructions are executed address 1000 interrupt may be accepted interrupt cannot be accepted address 1002 address 1004 address 1008 16-bit instruction 32-bit instruction interrupt may be accepted interrupt may be accepted eit 4.9 interrupt processing
4 4-19 ver.0.10 [eit processing] (1) saving sm, ie, and c bits the sm, ie, and c bits of the psw register are saved to their backup bits C the bsm, bie, and bc bits. bsm ? sm bie ? ie bc ? c (2) updating sm, ie, and c bits the sm, ie, and c bits of the psw register are updated as shown below. sm ? 0 ie ? 0 c ? 0 (3) saving pc the content (always word boundary) of the pc register is saved to the bpc register. (4) branching to the eit vector entry control branches to the address h'0000 0080 in the user space. however, when operating in flash e/w enable mode, control goes to the beginning of the internal ram (address h'0080 4000). (for details, refer to section 6.5, "writing to internal flash memory.") this is the last operation performed in hardware preprocessing by the m32r/e. (5) jumping from the eit vector entry to the user-created handler the m32r/e executes the "bra" instruction written at address h'0000 0080 of the eit vector entry by the user to jump to the start address of the user-created handler. at the beginning of the eit handler you created, first save the bpc and psw registers and the necessary general-purpose registers to the stack. (6) returning from the eit handler at the end of the eit handler, restore the general-purpose registers and the bpc and psw registers from the stack and then execute the "rte" instruction. as you execute the "rte" instruction, hardware postprocessing is automatically performed by the m32r/e. eit 4.9 interrupt processing
4 4-20 ver.0.10 4.10 trap processing 4.10.1 trap (trap) [occurrence conditions] traps refer to software interrupts which are generated by executing the "trap" instruction. sixteen distinct traps are generated, each corresponding to one of "trap" instruction operands 0-15. accordingly, sixteen vector entries are provided. [eit processing] (1) saving sm, ie, and c bits the sm, ie, and c bits of the psw register are saved to their backup bits C the bsm, bie, and bc bits. bsm ? sm bie ? ie bc ? c (2) updating sm, ie, and c bits the sm, ie, and c bits of the psw register are updated as shown below. unchanged sm ? 0 ie ? 0 c ? 0 (3) saving pc when the trap instruction is executed, the "pc value of the trap instruction + 4" is set in the bpc register. for example, if the "trap" instruction is located at address 4, the value h'08 is set in the bpc register. similarly, if the instruction is located at address 6, the value h'0a is set in the bpc register. in this case, the value of the bpc register bit 30 indicates whether the trap instruction resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the "rte" instruction returns after completion of processing by the eit handler is address 8. (this is because the two low-order bits are cleared to "00" when returning to the pc.) normally, when the program has been written in assembler, the halfword that immediately follows the "trap" instruction placed at a word boundary has the "nop" instruction automatically inserted by the assembler. eit 4.10 trap processing
4 4-21 ver.0.10 figure 4.10.1 example of a return address for trap (trap) (4) branching to the eit vector entry control branches to the addresses h'0000 0040 through h'0000 007c in the user space. this is the last operation performed in hardware preprocessing by the m32r/e. (5) jumping from the eit vector entry to the user-created handler the m32r/e executes the "bra" instruction written at addresses h'0000 0040 through h'0000 007c of the eit vector entry by the user to jump to the start address of the user- created handler. at the beginning of the eit handler you created, first save the bpc and psw registers and the necessary general-purpose registers to the stack. (6) returning from the eit handler at the end of the eit handler, restore the general-purpose registers and the bpc and psw registers from the stack and then execute the "rte" instruction. as you execute the "rte" instruction, hardware postprocessing is automatically performed by the m32r/e. h'00 h'04 h'08 h'0c +0 +1 +2 +3 h'00 h'04 h'08 h'0c +0 +1 +2 +3 bpc h'0a bpc h'08 address trap occurred return address ~ ~ ~ ~ return address address trap occurred ~ ~ ~ ~ eit 4.10 trap processing
4 4-22 ver.0.10 4.11 eit priority levels the table below lists the priority levels of eit events. when multiple eits occur simultaneously, the event with the highest priority is accepted first. table 4.11.1 priority of eit events and how returned from eit note that for external interrupt (ei), the priority levels of interrupt requests from each peripheral i/o are set by the 32170's internal interrupt controller. for details, refer to chapter 5, "interrupt controller." priority eit event type of processing values set in bpc register 1(highest) reset interrupt (ri) instruction processing indeterminate -aborted type address exception (ae) instruction processing- pc of the instruction that canceled type generated ae 2 reserved instruction instruction processing- pc of the instruction that exception (rie) canceled type generated ae trap (trap) instruction processing- trap instruction + 4 completed type 3 system break instruction processing- pc of the next instruction interrupt (sbi) completed type 4 external interrupt (ei) instruction processing- pc of the next instruction completed type eit 4.11 eit priority levels
4 4-23 ver.0.10 4.12 example of eit processing (1) when rie, ae, sbi, ei, or trap occurs singly figure 4.12.1 processing of events when rie, ae, sbi, ei, or trap occurs singly (2) when rie, ae, or trap and ei occurs simultaneously figure 4.12.2 processing of events when rie, ae, or trap and ei occurs simultaneously rte instruction ie=0 ie=1 bpc register = return address a ie=1 rie, ae, sbi, ei, or trap occurrs singly return address a: if ie = 0, no events but reset and sbi are accepted :eit handler rie, ae, or trap is accepted first bpc register = return address a rie, ae, or trap and ei occurs simultaneously ei is accepted next bpc register = return address a rte instruction ie=0 ie=1 ie=1 return address a: :eit handler ie=0 ie=1 rte instruction eit 4.12 example of eit processing
4 4-24 ver.0.10 figure 4.12.3 example of eit processing bra instruction rte eit handler eit vector entry program being executed save bpc to stack save psw to stack save general-purpose registers to stack processing by eit handler restore general- purpose registers restore psw restore bpc eit event occurs (sbi) system break interrupt processing program terminated or system reset (any event other than sbi) pc bpc psw (b)psw hardware preprocessing hardware postprocessing (b)psw psw bpc pc aa aa aaa aa ~ ~ ~ ~ eit 4.12 example of eit processing
chapter 5 chapter 5 interrupt controller (icu) 5.1 outline of the interrupt controller (icu) 5.2 interrupt sources of internal peripheral i/os 5.3 icu-related registers 5.4 icu vector table 5.5 description of interrupt operation 5.6 description of system break interrupt (sbi) operation
5 5-2 ver.0.10 interrupt controller (icu) 5.1 outline of the interrupt controller (icu) 5.1 outline of interrupt controller (icu) the interrupt controller (icu) manages maskable interrupts from internal peripheral i/os and a system break interrupt (sbi). the maskable interrupts from internal peripheral i/os are notified to the m32r cpu as external interrupts (ei). there are a total of 31 interrupt sources for the maskable interrupts from internal peripheral i/os, which are managed by assigning them one of eight priority levels including an interrupt-disabled state. when multiple interrupt requests of the same priority level occur simultaneously, their priorities are resolved by predetermined hardware priority. the source of an interrupt request generated in internal peripheral i/os is identified by reading the relevant interrupt status register provided for internal peripheral i/os. on the other hand, the system break interrupt (sbi) is recognized when a low-going transition _______ occurs on the sbi signal input pin. this interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the psw register ie bit status. when the icu has finished servicing an sbi, terminate or reset the system without returning to the program that was being executed when the interrupt occurred. specifications of the interrupt controller are outlined in the table below. table 5.1.1 outline of interrupt controller (icu) item specification interrupt source maskable interrupt from internal peripheral i/o : 31 sources system break interrupt : 1 source (entered from sbi pin) level management eight levels including an interrupt-disabled state (however, interrupts of the same level have their priorities resolved by fixed hardware priority.)
5 5-3 ver.0.10 interrupt controller (icu) 5.1 outline of the interrupt controller (icu) figure 5.1.1 block diagram of the interrupt controller interrupt vector register( ivect) interrupt mask register (imask) new_imask maskable interrupt request generated priority resolution by fixed hardware priority imask compar- ed ilevel priority resolution by interrupt priority levels set . . . . . . . system break interrupt request generated sbi ei sbi interrupt controller interrupt control register sbi control register (sbicr) sbireq ireq ireq ireq ireq ireq ireq peripheral circuits edge- recognized interrupt control circuit level- recognized interrupt request interrupt request interrupt request to the cpu core . . . . . . . . . edge- recognized edge- recognized level- recognized level- recognized interrupt control circuit interrupt control circuit to the cpu core
5 5-4 ver.0.10 5.2 interrupt sources of internal peripheral i/os the interrupt controller receives as its inputs the interrupt requests from mjt (multijunction timer), dmac, serial i/o, a-d converter, rtd, and can. for details about these interrupts, refer to each section in which the relevant internal peripheral i/o is described. table 5.2.1 interrupt sources of internal peripheral i/os (1/2) interrupt cause contents number of input icu type of input sources source(note) a-d0 conversion interrupt 1 edge-recognized a-d1 conversion interrupt 1 edge-recognized sio0 transmit interrupt 1 edge-recognized sio0 receive interrupt 1 edge-recognized sio1transmit interrupt 1 edge-recognized sio1 receive interrupt 1 edge-recognized sio2,3 transmit/receive 4 level-recognized interrupt sio4,5 transmit/receive 4 level-recognized interrupt tid0 output interrupt 1 edge-recognized tid1 output interrupt 1 edge-recognized tid2 output interrupt 1 edge-recognized tod0 output interrupt 8 level-recognized tod1 + tom0 output 16 level-recognized interrupt tml1 input interrupt 4 level-recognized rtd interrupt 1 edge-recognized dma transfer interrupt 0 5 level-recognized dma transfer interrupt 1 5 level-recognized can0 transmit/receive 5 level-recognized & error interrupt note: icu type of input source ? edge-recognized: interrupt requests are generated on a falling edge of the interrupt signal applied to the icu. ? level-recognized: interrupt requests are generated when the interrupt signal applied to the icu is held low. for these level-recognized interrupts, the icu's interrupt control register irq bit cannot be set or cleared in software. single-shot conversion in a-d0 converter scan mode completed, single mode completed, or comparator mode completed single-shot conversion in a-d1 converter scan mode completed, single mode completed, or comparator mode completed sio0 transmit buffer empty interrupt sio0 reception completed or receive error interrupt sio1 transmit buffer empty interrupt sio1 reception completed or receive error interrupt sio2, 3 reception completed or receive error interrupt transmit buffer empty interrupt sio4, 5 reception completed or receive error interrupt transmit buffer empty interrupt tid0 output tid1 output tid2 output tod0_0 to tod0_7 output tod1_0 to tod1_7 output + tom0_0 to tom0_7 output tml1 input (tin30 to tin33 input) rtd interrupt generation command dma0-4 transfer completed dma5-9 transfer completed can0 transmission completed, can0 reception completed, can0 error passive, can0 error bus-off, can0 bus error interrupt controller (icu) 5.2 interrupt sources of internal peripheral i/os
5 5-5 ver.0.10 table 5.2.2 interrupt sources of internal peripheral i/os (2/2) interrupt source content number of input icu type of input sources source (note) mjt output interrupt 7 mjt output interrupt group 7 (tms0, tms1 output) 2 level-recognized mjt output interrupt 6 mjt output interrupt group 6 (top8, top9 output) 2 level-recognized mjt output interrupt 5 mjt output interrupt group 5 (top10 output) 1 edge-recognized mjt output interrupt 4 mjt output interrupt group 4 (tio4 - tio7 output) 4 level-recognized mjt output interrupt 3 mjt output interrupt group 3 (tio8, tio9 output) 2 level-recognized mjt output interrupt 2 mjt output interrupt group 2 (top0 - top5 output) 6 level-recognized mjt output interrupt 1 mjt output interrupt group 1 (top6, top7 output) 2 level-recognized mjt output interrupt 0 mjt output interrupt group 0 (tio0 - tio3 output) 4 level-recognized mjt input interrupt 4 mjt input interrupt group 4 (tin3-tin6 input) 4 level-recognized mjt input interrupt 3 mjt input interrupt group 3 (tin20-tin23 input) 4 level-recognized mjt input interrupt 2 mjt input interrupt group 2 (tin12-tin19 input) 8 level-recognized mjt input interrupt 1 mjt input interrupt group 1 (tin0-tin2 input) 3 level-recognized mjt input interrupt 0 mjt input interrupt group 0 (tin7-tin11 input) 5 level-recognized note: icu type of input source ? edge-recognized: interrupt requests are generated on a falling edge of the interrupt signal applied to the icu. ? level-recognized: interrupt requests are generated when the interrupt signal applied to the icu is held low. for these level-recognized interrupts, the icu's interrupt control register irq bit cannot be set or cleared in software. interrupt controller (icu) 5.2 interrupt sources of internal peripheral i/os
5 5-6 ver.0.10 5.3 icu-related registers the diagram below shows a map of the interrupt controller (icu)'s related registers. figure 5.3.1 interrupt controller (icu) related register map interrupt controller (icu) 5.3 icu-related registers h'0080 0000 address d0 d7 +0 address +1 address d8 d15 h'0080 0004 h'0080 0006 h'0080 0066 h'0080 0068 aaaaaaa aaaaaaa interrupt mask register (imask) sbi control register (sbicr) h'0080 006a h'0080 006c h'0080 006e h'0080 0070 h'0080 0072 h'0080 0074 h'0080 0076 h'0080 0078 aaaaaaa h'0080 0002 h'0080 007a h'0080 007c h'0080 007e a-d0 conversion interrupt control register (iad0ccr) sio0 receive interrupt control register (isio0rxcr) sio1 receive interrupt control register (isio1rxcr) sio1 transmit interrupt control register (isio1txcr) sio0 transmit interrupt control register (isio0txcr) dma0-4 interrupt control register (idma04cr) mjt output interrupt control register 0 (imjtocr0) mjt output interrupt control register 2 (imjtocr2) mjt output interrupt control register 4 (imjtocr4) mjt output interrupt control register (imjtocr6) mjt output interrupt control register (imjtocr1) mjt output interrupt control register 3 (imjtocr3) mjt output interrupt control register5 (imjtocr5) mjt output interrupt control register7 (imjtocr7) mjt input interrupt control register 0 (imjticr0) mjt input interrupt control register 1 (imjticr1) mjt input interrupt control register 2 (imjticr2) mjt input interrupt control register 3 (imjticr3) mjt input interrupt control register 4 (imjticr4) tid1 output interrupt control register (itid1cr) sio2,3 transmit/receive interrupt control register (isio23cr) rtd interrupt control register (irtdcr) dma5-9 interrupt control register (idma59cr) tod0 output interrupt control register (itod0cr) tid0 output interrupt control register (itid0cr) interrupt vector register (ivect) note: the registers in the thick frames must always be accessed in halfwords. h'0080 0060 can0 transmit/receive & error interrupt control register (ican0cr) tml1 input interrupt control register (itml1cr) h'0080 0062 tid2 output interrupt control register (itid2cr) a-d1 conversion interrupt control register (iad1ccr) h'0080 0064 sio4,5 transmit/receive interrupt control register (isio45cr) tod1+tom0 output interrupt control register (itom0cr) blank addresses are reserved for future use. ~ ~ ~ ~
5 5-7 ver.0.10 5.3.1 interrupt vector register n interrupt vector register (ivect) d bit name function r w 0 C 15 ivect (16 low-order when an interrupt is accepted, the 16 low-order bits C bits of icu vector in icu vector table address for the accepted table address) interrupt source is stored in this register. note: this register must always be accessed in halfwords. the interrupt vector register (ivect) is used when an interrupt is accepted to store the 16 low- order bits of icu vector table address for the accepted interrupt source. before this function can work, the icu vector table (addresses h'0000 0094 through h'0000 010f) must have set in it the start addresses of interrupt handlers for each internal peripheral i/o. when an interrupt is accepted, the 16 low-order bits of icu vector table address for the accepted interrupt source is stored in this ivect register. the eit handler reads out the content of the ivect register by the "ldh" instruction to acquire the icu vector table address. when the ivect register is read out, operations (1) to (4) below are automatically performed in hardware: (1) the accepted new imask (new_imask) is set in the imask register. (2) the accepted interrupt request is cleared (not cleared for level-recognized interrupt sources). (3) the interrupt request (ei) to the cpu core is cleared. (4) the icu's internal sequencer is activated to start internal processing (interrupt priority resolution). note that the interrupt vector register (ivect) can only be read out by the eit handler (psw register ie bit being disabled). also, make sure that in the eit handler, the interrupt mask register (imask) is read out before reading out the ivect register. caution d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 ivect interrupt controller (icu) 5.3 icu-related registers
5 5-8 ver.0.10 5.3.2 interrupt mask register n interrupt mask register (imask) the interrupt mask register (imask) is used to finally determine whether an interrupt request can be accepted after comparing its priority with the priority levels that have been set for each interrupt source (by setting the interrupt control register ilevel bits). when the interrupt vector register (ivect) described above is read out, a new mask value (new_imask) is set in this imask register. when any value is written to the imask register, operations (1) to (2) below are automatically performed in hardware: (1) the interrupt request (ei) to the cpu core is cleared. (2) the icu's internal sequencer is activated to start internal processing (interrupt priority resolution). note that the interrupt mask register (imask) can only be read out by the eit handler (psw register ie bit being disabled). d bit name function r w 0 C 4 no functions assigned 0 C 5C 7 imask (interrupt mask) 000 : maskable interrupts are disabled 001 : level 0 interrupts can be accepted 010 : level 0-1 interrupts can be accepted 011 : level 0-2 interrupts can be accepted 100 : level 0-3 interrupts can be accepted 101 : level 0-4 interrupts can be accepted 110 : level 0-5 interrupts can be accepted 111 : level 0-6 interrupts can be accepted d0123456d7 imask interrupt controller (icu) 5.3 icu-related registers caution
5 5-9 ver.0.10 5.3.3 sbi (system break interrupt) control register n sbi (system break interrupt) control register w = : writable for only clearing operation (see the description below) _______ the sbi (system break interrupt) is an interrupt generated by a falling edge on sbi signal input pin. when an sbi occurs, the sbi control register's sbireq (sbi request) bit is set to 1. the sbireq bit cannot be set in software. to clear the sbireq bit after being set, perform the operation described below. (be careful not to clear this bit when no sbi request has been generated.) ? write a 1 and then a 0 to sbireq. d bit name function r w 0 C 6 no functions assigned 0 C 7 sbi req (sbi request) 0 : sbi is not requested 1 : sbi is requested d0123456d7 sbireq interrupt controller (icu) 5.3 icu-related registers
5 5-10 ver.0.10 5.3.4 interrupt control registers n can0 transmit/receive & error interrupt control register (ican0cr) n tml1 interrupt control register (itml1cr) n tid2 output interrupt control register (itid2cr) n a-d1 converter interrupt control register (iad1ccr) n sio4,5 transmit/receive interrupt control register (isio45cr) n tod1+tom0 output interrupt control register (itom0cr) n tid1 output interrupt control register (itid1cr) n rtd interrupt control register (irtdcr) n sio2,3 transmit/receive interrupt control register (isio23cr) n dma5-9 interrupt control register (idma59cr) n tod0 output interrupt control register (itod0cr) n tid0 output interrupt control register (itid0cr) n a-d0 converter interrupt control register (iad0ccr) n sio0 transmit interrupt control register (isio0txcr) n sio0 receive interrupt control register (isio0rxcr) n sio1 transmit interrupt control register (isio1txcr) n sio1 receive interrupt control register (isio1rxcr) n dma0-4 interrupt control register (idma04cr) n mjt output interrupt control register 0 (imjtocr0) n mjt output interrupt control register 1 (imjtocr1) n mjt output interrupt control register 2 (imjtocr2) n mjt output interrupt control register 3 (imjtocr3) n mjt output interrupt control register 4 (imjtocr4) n mjt output interrupt control register 5 (imjtocr5) n mjt output interrupt control register 6 (imjtocr6) n mjt output interrupt control register 7 (imjtocr7) n mjt input interrupt control register 0 (imjticr0) n mjt input interrupt control register 1 (imjticr1) n mjt input interrupt control register 2 (imjticr2) n mjt input interrupt control register 3 (imjticr3) n mjt input interrupt control register 4 (imjticr4) interrupt controller (icu) 5.3 icu-related registers
5 5-11 ver.0.10 w= : can be set and cleared only when the type of input source is "edge-recognized" type (with only one interrupt source being input). (1) ireq (interrupt request) bit (d3 or d11) when an interrupt request from some internal peripheral i/o occurs, the corresponding ireq (interrupt request) bit is set to 1. this bit can be set and cleared in software for only edge-recognized interrupt sources (and not for level-recognized interrupt sources). also, when the ireq bit is set by an interrupt request generated by an edge-recognized interrupt source, it is automatically cleared to 0 by reading out the interrupt vector register (ivect) (not cleared in the case of level-recognized interrupt sources). if the ireq bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. also, if the ireq bit is cleared by reading out the ivect register at the same time it is set by an interrupt request generated, clearing by a read of ivect has priority. d bit name function r w 0 C 2 no functions assigned 0 C (8-10) 3 ireq (interrupt request) 0 : interrupt is not requested (11) 1 : interrupt is requested 4 no functions assigned 0 C (12) 5-7 ilevel (interrupt priority level) 000 : interrupt priority level 0 (13-15) 001 : interrupt priority level 1 010 : interrupt priority level 2 011 : interrupt priority level 3 100 : interrupt priority level 4 101 : interrupt priority level 5 110 : interrupt priority level 6 111 : interrupt priority level 7 (interrupt-disabled state) d0123456d7 ( d8 9 10 11 12 13 14 d15) ireq ilevel interrupt controller (icu) 5.3 icu-related registers
5 5-12 ver.0.10 figure 5.3.2 interrupt control register configuration (edge-recognized type) figure 5.3.3 interrupt control register configuration (level-recognized type) interrupt controller (icu) 5.3 icu-related registers interrupt priority resolving circuit interrupt request from each peripheral function interrupt enabled ilevel (levels 0-7) d3,11 data bus d5-7,13-15 3 f/f set set/clear ireq d3,11 d5-7,13-15 rd 3 ireq group interrupt interrupt priority resolving circuit group interrupt request from each peripheral function interrupt enabled ilevel (levels 0-7) data bus read-only circuit
5 5-13 ver.0.10 (2) ilevel (interrupt priority level) (d5-d7 or d13-d15) these bits set the priority levels of interrupt requests from each internal peripheral i/o. set priority level 7 to disable interrupts from some internal peripheral i/o or priority levels 0-6 to enable interrupts. when an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ilevel settings and finally compares its priority with the imask value to determine whether to forward an ei request to the cpu or keep it pending. the table below shows the relationship between ilevel settings and the imask values at which interrupts are accepted. table 5.3.1 ilevel settings and accepted imask values ilevel values set imask values at which interrupts are accepted 0 (ilevel="000") accepted when imask is 1-7 1 (ilevel="001") accepted when imask is 2-7 2 (ilevel="010") accepted when imask is 3-7 3 (ilevel="011") accepted when imask is 4-7 4 (ilevel="100") accepted when imask is 5-7 5 (ilevel="101") accepted when imask is 6-7 6 (ilevel="110") accepted when imask is 7 7 (ilevel="111") not accepted (interrupts disabled) interrupt controller (icu) 5.3 icu-related registers
5 5-14 ver.0.10 5.4 icu vector table the icu vector table is used to set the start addresses of interrupt handlers for each internal peripheral i/o. the 31-source interrupts are assigned the following addresses: table 5.4.1 icu vector table addresses interrupt source icu vector table address mjt input interrupt 4 h'0000 0094-h'0000 0097 mjt input interrupt 3 h'0000 0098-h'0000 009b mjt input interrupt 2 h'0000 009c-h'0000 009f mjt input interrupt 1 h'0000 00a0-h'0000 00a3 mjt input interrupt 0 h'0000 00a4-h'0000 00a7 mjt output interrupt 7 h'0000 00a8-h'0000 00ab mjt output interrupt 6 h'0000 00ac-h'0000 00af mjt output interrupt 5 h'0000 00b0-h'0000 00b3 mjt output interrupt 4 h'0000 00b4-h'0000 00b7 mjt output interrupt 3 h'0000 00b8-h'0000 00bb mjt output interrupt 2 h'0000 00bc-h'0000 00bf mjt output interrupt 1 h'0000 00c0-h'0000 00c3 mjt output interrupt 0 h'0000 00c4-h'0000 00c7 dma0-4 interrupt h'0000 00c8-h'0000 00cb sio1 receive interruptt h'0000 00cc-h'0000 00cf sio1 transmit interruptt h'0000 00d0-h'0000 00d3 sio0 receive interruptt h'0000 00d4-h'0000 00d7 sio0 transmit interruptt h'0000 00d8-h'0000 00db a-d0 converter interruptt h'0000 00dc-h'0000 00df tid0 output interruptt h'0000 00e0-h'0000 00e3 tod0 output interruptt h'0000 00e4-h'0000 00e7 dma5-9 interruptt h'0000 00e8-h'0000 00eb sio2,3 transmit/receive interrupt t h'0000 00ec-h'0000 00ef rtd interruptt h'0000 00f0-h'0000 00f3 tid1 output interrupt h'0000 00f4-h'0000 00f7 tod1+tom0 output interrupt h'0000 00f8-h'0000 00fb sio4,5 transmit/receive interrupt h'0000 00fc-h'0000 00ff a-d1 converter interrupt h'0000 0100-h'0000 0103 tid2 output interrupt h'0000 0104-h'0000 0107 tml1 input interrupt h'0000 0108-h'0000 010b can0 transmit/receive & error interrupt h'0000 010c-h'0000 010f interrupt controller (icu) 5.4 icu vector table
5 5-15 ver.0.10 figure 5.4.1 icu vector table memory map (1/2) h'0000 0094 address d0 d7 +0 address +1 address d8 d15 h'0000 0096 mjt input interrupt 4 handler start address (a0-a15) mjt input interrupt 4 handler start address (a16-a31) h'0000 0098 h'0000 009a mjt input interrupt 3 handler start address (a0-a15) mjt input interrupt 3 handler start address (a16-a31) h'0000 009c h'0000 009e mjt input interrupt 2 handler start address (a0-a15) mjt input interrupt 2 handler start address (a16-a31) h'0000 00a0 h'0000 00a2 mjt input interrupt 1 handler start address (a0-a15) mjt input interrupt 1 handler start address (a16-a31) h'0000 00a4 h'0000 00a6 h'0000 00a8 h'0000 00aa h'0000 00ac h'0000 00ae h'0000 00b0 h'0000 00b2 h'0000 00b4 h'0000 00b6 h'0000 00b8 h'0000 00ba h'0000 00bc h'0000 00be h'0000 00c0 h'0000 00c2 h'0000 00c4 h'0000 00c6 mjt output interrupt 7 handler start address (a0-a15) mjt output interrupt 7 handler start address (a16-a31) mjt output interrupt 6 handler start address (a0-a15) mjt output interrupt 6 handler start address (a16-a31) mjt output interrupt 5 handler start address (a0-a15) mjt output interrupt 5 handler start address (a16-a31) mjt output interrupt 4 handler start address (a0-a15) mjt output interrupt 4 handler start address (a16-a31) mjt output interrupt 3 handler start address (a0-a15) mjt output interrupt 3 handler start address (a16-a31) mjt output interrupt 2 handler start address (a0-a15) mjt output interrupt 2 handler start address (a16-a31) mjt output interrupt 1 handler start address (a0-a15) mjt output interrupt 1 handler start address (a16-a31) mjt output interrupt 0 handler start address (a0-a15) mjt output interrupt 0 handler start address (a16-a31) mjt input interrupt 0 handler start address (a0-a15) mjt input interrupt 0 handler start address (a16-a31) interrupt controller (icu) 5.4 icu vector table
5 5-16 ver.0.10 figure 5.4.2 icu vector table memory map (2/2) h'0000 00c8 address d0 d7 +0 address +1 address d8 d15 h'0000 00ca dma0-4 interrupt handler start address (a0-a15) dma0-4 interrupt handler start address (a16-a31) h'0000 00cc h'0000 00ce h'0000 00d0 h'0000 00d2 h'0000 00d4 h'0000 00d6 h'0000 00d8 h'0000 00da h'0000 00dc h'0000 00de sio1 receive interrupt handler start address (a0-a15) sio1 receive interrupt handler start address (a16-a31) sio1 transmit interrupt handler start address (a0-a15) sio1 transmit interrupt handler start address (a16-a31) sio0 receive interrupt handler start address (a0-a15) sio0 receive interrupt handler start address (a16-a31) sio0 transmit interrupt handler start address (a0-a15) sio0 transmit interrupt handler start address (a16-a31) a-d0 converter interrupt handler start address (a0-a15) a-d0 converter interrupt handler start address (a16-a31) h'0000 00e0 h'0000 00e2 h'0000 00e4 h'0000 00e6 h'0000 00e8 h'0000 00ea h'0000 00ec h'0000 00ee tid0 input interrupt handler start address (a0-a15) tid0 input interrupt handler start address (a16-a31) tod0 output interrupt handler start address (a0-a15) tod0 output interrupt handler start address (a16-a31) dma5-9 interrupt handler start address (a0-a15) dma5-9 interrupt handler start address (a16-a31) sio2,3 transmit/receive interrupt handler start address (a0-a15) sio2,3 transmit/receive interrupt handler start address (a16-a31) h'0000 00f0 h'0000 00f2 rtd interrupt handler start address (a0-a15) rtd interrupt handler start address (a16-a31) h'0000 00f4 h'0000 00f6 tid1 input interrupt handler start address (a0-a15) tid1 input interrupt handler start address (a16-a31) h'0000 00f8 h'0000 00fa tod1+tom0 output interrupt handler start address (a0-a15) tod1+tom0 output interrupt handler start address (a16-a31) h'0000 00fc h'0000 00fe sio4,5 transmit/receive interrupt handler start address (a0-a15) sio4,5 transmit/receive interrupt handler start address (a16-a31) h'0000 0100 h'0000 0102 a-d1 converter interrupt handler start address (a0-a15) a-d1 converter interrupt handler start address (a16-a31) h'0000 0104 h'0000 0106 tid2 input interrupt handler start address (a00-a15) tid2 input interrupt handler start address (a16-a31) h'0000 0108 h'0000 010a tml1 input interrupt handler start address (a00-a15) tml1 input interrupt handler start address (a16-a31) h'0000 010c h'0000 010e can0 transmit/receive & error interrupt handler start address (a0-a15) can0 transmit/receive & error interrupt handler start address (a16-a31) interrupt controller (icu) 5.4 icu vector table
5 5-17 ver.0.10 5.5 description of interrupt operation 5.5.1 acceptance of internal peripheral i/o interrupts an interrupt from any internal peripheral i/o is checked to see whether or not to accept by comparing its ilevel value set by the interrupt control register and the imask value of the interrupt mask register. if its priority is higher than the imask value, the interrupt is accepted. however, when multiple interrupt requests occur simultaneously, the interrupt controller resolves priority between these interrupt requests following the procedure described below. the ilevel values set by the interrupt control register for each interrupt peripheral i/o are compared with each other. if the ilevel values are the same, they are resolved according to the predetermined hardware priority. a the ilevel value is compared with imask value. when multiple interrupt requests occur simultaneously, the interrupt controller first compares their priority levels set by each interrupt control register's ilevel bit to select an interrupt request which has the highest priority. if the interrupt requests have the same level value, they are resolved according to the hardware-fixed priority. the interrupt request thus selected has its ilevel value compared with imask value and if its priority is higher than the imask value, the interrupt controller sends an ei request to the cpu. interrupt requests may be masked by setting the interrupt mask register and the interrupt control register's ilevel bit (level 7 = disabled) provided for each internal peripheral i/o and the psw register ie bit. figure 5.5.1 example of priority resolution when accepting interrupt interrupt requested or not resolve priority according to interrupt priority levels (ilevel) resolve priority according to hardware priority compare with imask value mjt output interrupt 4 mjt output interrupt 3 mjt output interrupt 2 mjt output interrupt 1 dma0-4 interrupt a-d0 converter interrupt (ilevel settings) level 3 level 4 level 5 level 3 level 1 level 3 not requested requested requested requested requested requested hardware-fixed priority accept interrupt if psw register ie bit = 1 level 3 level 3 level 3 1 2 3 can be accepted when imask = 4-7 interrupt controller (icu) 5.5 description of interrupt operation
5 5-18 ver.0.10 table 5.5.1 hardware-fixed priority levels priority interrupt source icu vector table address type of input source high mjt input interrupt 4 (irq12) h'0000 0094-h'0000 0097 level-recognized mjt input interrupt 3 (irq11) h'0000 0098-h'0000 009b level-recognized mjt input interrupt 2 (irq10) h'0000 009c-h'0000 009f level-recognized mjt input interrupt 1 (irq9) h'0000 00a0-h'0000 00a3 level-recognized mjt input interrupt 0 (irq8) h'0000 00a4-h'0000 00a7 level-recognized mjt output interrupt 7 (irq7) h'0000 00a8-h'0000 00ab level-recognized mjt output interrupt 6 (irq6) h'0000 00ac-h'0000 00af level-recognized mjt output interrupt 5 (irq5) h'0000 00b0-h'0000 00b3 edge-recognized mjt output interrupt 4 (irq4) h'0000 00b4-h'0000 00b7 level-recognized mjt output interrupt 3 (irq3) h'0000 00b8-h'0000 00bb level-recognized mjt output interrupt 2 (irq2) h'0000 00bc-h'0000 00bf level-recognized mjt output interrupt 1 (irq1) h'0000 00c0-h'0000 00c3 level-recognized mjt output interrupt 0 (irq0) h'0000 00c4-h'0000 00c7 level-recognized dma0-4 interrupt h'0000 00c8-h'0000 00cb level-recognized sio1 receive interrupt h'0000 00cc-h'0000 00cf edge-recognized sio1 transmit interrupt h'0000 00d0-h'0000 00d3 edge-recognized sio0 receive interrupt h'0000 00d4-h'0000 00d7 edge-recognized sio0 transmit interrupt h'0000 00d8-h'0000 00db edge-recognized a-d0 converter interrupt h'0000 00dc-h'0000 00df edge-recognized tid0 output interrupt h'0000 00e0-h'0000 00e3 edge-recognized tod0 output interrupt h'0000 00e4-h'0000 00e7 level-recognized dma5-9 interrupt h'0000 00e8-h'0000 00eb level-recognized sio2,3 transmit/receive interrupt h'0000 00ec-h'0000 00ef level-recognized rtd interrupt h'0000 00f0-h'0000 00f3 edge-recognized tid1 output interrupt h'0000 00f4-h'0000 00f7 edge-recognized tod1+tom0 output interrupt h'0000 00f8-h'0000 00fb level-recognized sio4,5 transmit/receive interrupt h'0000 00fc-h'0000 00ff level-recognized a-d1 converter interrupt h'0000 0100-h'0000 0103 edge-recognized tid2 output interrupt h'0000 0104-h'0000 0107 edge-recognized tml1 input interrupt h'0000 0108-h'0000 010b level-recognized low can0 transmit/receive & error interrupt h'0000 010c-h'0000 010f level-recognized interrupt controller (icu) 5.5 description of interrupt operation
5 5-19 ver.0.10 table 5.5.2 ilevel settings and accepted imask values ilevel values set imask values at which interrupts are accepted 0 (ilevel="000") accepted when imask is 1-7 1 (ilevel="001") accepted when imask is 2-7 2 (ilevel="010") accepted when imask is 3-7 3 (ilevel="011") accepted when imask is 4-7 4 (ilevel="100") accepted when imask is 5-7 5 (ilevel="101") accepted when imask is 6-7 6 (ilevel="110") accepted when imask is 7 7 (ilevel="111") not accepted (interrupts disabled) interrupt controller (icu) 5.5 description of interrupt operation
5 5-20 ver.0.10 5.5.2 processing of internal peripheral i/o interrupts by handlers (1) branching to the interrupt handler when the cpu accepts an interrupt, control branches to the eit vector entry after hardware preprocessing as described in section 4.3, "eit processing procedure." the eit vector entry for external interrupt (ei) is located at address h'0000 0080. this address is where the instruction (not the jump address) for branching to the beginning of the interrupt processing routine for external interrupt (ei) is written. (2) processing by interrupt handler in the external interrupt (ei) handler, first save the bpc register, psw register, and general- purpose registers to the stack. next, read out the interrupt mask register (imask) and save the read value to the stack. then read out the interrupt vector register (ivect). always be sure to read out the imask before reading the ivect. a read of imask and that of ivect both triggers an operation to clear interrupt requests to the cpu and accept the next interrupt. furthermore, a read of ivect causes new_imask to be set in the imask and the accepted interrupt request to be cleared (not cleared in the case of level-recognized interrupt sources, however). the ivect register has set in it the 16 low-order bits of icu vector table address for the accepted interrupt source. read the ivect register using a signed halfword load instruction (ldh instruction) and then the content of the icu interrupt vector table indicated by the read address. make sure the icu vector table has the start addresses of interrupt handlers for each internal peripheral i/o written in it beforehand, so that control will branch to the address read from this table to execute processing by each handler. when returning from the handler, clear the psw register ie bit to 0 to disable interrupts and then restore the imask value from the stack. (3) identifying the source of interrupt generated if any internal peripheral i/o has multiple interrupt sources, check the interrupt status register for each internal peripheral i/o to identify the source of interrupt generated. (4) enabling multiple interrupts to enable another interrupt in an interrupt handler, set the psw register's ie (interrupt enable) bit to 1 to enable interrupts so that they will be accepted. however, before writing a 1 to the ie bit, always be sure to save each register (bpc, psw, general-purpose register, and imask) to the stack. interrupt controller (icu) 5.5 description of interrupt operation
5 5-21 ver.0.10 figure 5.5.2 typical operation for interrupts from internal peripheral i/o h'0000 0080 bra instruction read interrupt vector register (ivect) read icu vector table branch to interrupt handler for each internal peripheral i/o rte h'0080 0004 h'0000 0094 h'0000 010f . . . interrupt handler ei (external interrupt) handler ei (external interrupt) vector entry address program being executed interrupt generated ivect . . . . . . save bpc to stack save psw to stack save general-purpose register to stack restore bpc restore psw restore general- purpose register read interrupt mask register (imask) and save it to stack imask h'0080 0000 psw register ie bit = 1 psw register ie bit = 0 restore interrupt mask register (imask) 1 2 3 4 6 7 8 5 9 10 10 1 - 8 5 : processing of ei by interrupt handler : when enabling multiple interrupts . . . . . . icu vector table note: for operations performed when accepting eit and returning from handlers, also refer to section 4.3, "eit processing procedure." (note) (note) interrupt handler interrupt controller (icu) 5.5 description of interrupt operation
5 5-22 ver.0.10 5.6 description of system break interrupt (sbi) operation 5.6.1 acceptance of sbi system break interrupt (sbi) is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. the system break interrupt is _______ accepted anytime upon detection of a falling edge on the sbi signal regardless of how the psw register ie bit is set, and cannot be masked. 5.6.2 sbi processing by handler when the system break interrupt generated has been serviced, always be sure to terminate or reset the system without returning to the program that was being executed when the interrupt occurred. figure 5.6.1 typical sbi operation h'0000 0010 bra instruction sbi (system break interrupt) handler sbi (system break interrupt) vector entry program being executed sbi generated . . . . . . processing to terminate the system note: do not return to the program that was being executed when the interrupt occurred. terminate or reset the system interrupt controller (icu) 5.6 description of system break interrupt (sbi) operation
chapter 6 chapter 6 internal memory 6.1 outline of the internal memory 6.2 internal ram 6.3 internal flash memory 6.4 registers associated with the internal flash memory 6.5 programming of the internal flash memory 6.6 boot rom 6.7 virtual flash emulation function 6.8 connecting to a serial programmer 6.9 precautions to be taken when rewriting flash memory
6 6-2 ver.0.10 6.1 outline of the internal memory the 32170 internally contains the following types of memory: ? 40 kbyte or 32 kbyte ram ? 768 kbyte, 512 kbyte, or 384 kbyte flash memory 6.2 internal ram specifications of the 32170's internal ram are shown below. table 6.2.1 specifications of the internal ram item specification capacity m32170f6 : 40 kbytes m32170f4, m32170f3 : 32kbytes location address m32170f6 : h'0080 4000 - h'0080 dfff m32170f4, m32170f3 : h'0080 4000 - h'0080 bfff wait insertion operates with no wait states (when using 40 mhz cpu clock) internal bus connection connected by 32-bit bus dual port by using the real-time debugger (rtd), data can be read (monitored) or written to any area of the internal ram via serial communication from external devices independently of the cpu. (refer to chapter 14, "real-time debugger.") 6.3 internal flash memory specifications of the 32170's internal flash memory are shown below. table 6.3.1 specifications of the internal flash memory item specification capacity m32170f6 : 768 kbytes m32170f4 : 512kbytes m32170f3 : 384kbytes location address m32170f6 : h'0000 0000 - h'000b ffff m32170f4 : h'0000 0000 - h'0007 ffff m32170f3 : h'0000 0000 - h'0005 ffff wait insertion operates with no wait states (when using 40 mhz cpu clock) durability can be rewritten 100 times internal bus connection connected by 32-bit bus other virtual flash emulation function is included. (refer to section 6.7, "virtual flash emulation function.") internal memory 6.1 outline of the internal memory
6 6-3 ver.0.10 internal memory 6.4 registers associated with the internal flash memory 6.4 registers associated with the internal flash memory the diagram below shows a register map associated with the internal flash memory. figure 6.4.1 register map associated with the internal flash memory h'0080 07e0 h'0080 07e2 address d0 d7 +0 address +1 address d8 d15 h'0080 07e4 h'0080 07e6 h'0080 07e8 h'0080 07ea h'0080 07ec h'0080 07ee h'0080 07f0 h'0080 07f2 blank addresses are reserved for future use. (note) note: the m32170f4 and m32170f3 do not have the felbank3 register. flash mode register (fmod) flash controle register 1 (fcnt1) flash controle register 3 (fcnt3) flash status register 1 (fstat1) flash controle register 2 (fcnt2) flash controle register 4 (fcnt4) virtual flash l bank register 0 (felbank0) virtual flash l bank register 1 (felbank1) virtual flash l bank register 2 (felbank2) virtual flash l bank register 3 (felbank3) virtual flash s bank register 0 (fesbank0) virtual flash s bank register 1 (fesbank1)
6 6-4 ver.0.10 d0123456d7 fpmod d bit name function r w 0 - 6 no functions assigned 0 7 fpmod 0 : fp pin = low (external fp pin status) 1 : fp pin = high the flash mode register (fmod) is a read-only status register, with its fpmod bit indicating the status of the fp (flash protect) pin. write to the flash memory is enabled only when fpmod = 1. writing to the flash memory when fpmod = 0 has no effect. 6.4.1 flash mode register n flash mode register (fmod) internal memory 6.4 registers associated with the internal flash memory
6 6-5 ver.0.10 internal memory 6.4 registers associated with the internal flash memory 6.4.2 flash status registers the 32170 has two registers to indicate the flash memory status, one of which is flash status register 1 (fstat1) located in the sfr area (address: h'0080 07e1), and the other is flash status register 2 (fstat2) included in the flash memory itself. when programming or erasing the flash memory, use these two status registers (fstat1, fstat2) to control the program/erase operations. n flash status register 1 (fstat1) d8 9 1011121314d15 fstat d bit name function r w 8 - 14 no functions assigned 0 15 fstat 0 : busy (ready/busy status) 1 : ready the flash status register 1 (fstat1) is a read-only status register used to know the execution status of whether the flash memory is being programmed or erased. when the fstat bit = 0, it means that the flash memory is being programmed or erased, during which time any operation to program the flash memory area is disabled.
6 6-6 ver.0.10 n flash status register 2 (fstat2) d8 9 1011121314d15 fbusy erase wrerr1 wrerr2 d bit name function r w 8 fbusy 0 : program or erase under way (flash busy) 1 : ready state 9 no functions assigned 0 10 erase 0 : erase normally operating/terminated (auto erase operating condition) 1 : erase error occurred 11 wrerr1 0 : program normally operating/terminated (program operating condition) 1 : program error occurred 12 wrerr2 0 : program normally operating/terminated (program operating condition) 1 : over-programming occurred 13 - 15 no functions assigned 0 the flash status register 2 (fstat2) consists of the following four read-only status bits which indicate the operating condition of the flash memory. (1) fbusy (flash busy) bit (d8) the fbusy bit is used to determine whether the operation is terminated when programming or erasing the flash memory. when fbusy = 0, it means the program or erase operation is being executed; when fbusy = 1, the operation is terminated. (2) erase (auto erase operating condition) bit (d10) the erase bit is used to determine whether execution of the flash memory erase operation has resulted in an error. when erase = 0, it means the erase operation terminated normally; when erase = 1, the operation terminated in an error. (3) wrerr1 (program operating condition) bit (d11) the wrerr1 bit is used to determine after completion of execution whether the flash memory program operation resulted in an error. when wrerr1 = 0, it means the program operation terminated normally; when wrerr1 = 1, the operation terminated in an error. the condition under which wrerr1 is set to 1 is when any bit other than those that must be 0 is found to be a 0 by comparison between the write data and the data in the flash memory. internal memory 6.4 registers associated with the internal flash memory
6 6-7 ver.0.10 internal memory 6.4 registers associated with the internal flash memory (4) wrerr2 (program operating condition) bit (d12) the wrerr2 bit is used to determine after execution whether the flash memory program operation resulted in an error. when wrerr2 = 0, it means the program operation terminated normally; when wrerr2 = 1, the operation terminated in an error. the condition under which wrerr2 is set to 1 is when the flash memory could not be written to by repeating the write operation a specified number of times. note: this status register is included in the internal flash memory itself, and can be read out by writing the read status command (h'7070) to any address of the flash memory. for details, refer to section 6.5, "programming of internal flash memory."
6 6-8 ver.0.10 d0123456d7 fentry femmod d bit name function r w 0 - 2 no functions assigned 0 3 fentry 0 : normal read (flash mode entry) 1 : erase/program enable 4 - 6 no functions assigned 0 7 femmod 0 : normal mode (virtual flash emulation mode) 1 : virtual flash emulation mode the flash control register 1 (fcnt1) consists of the following two bits to control the internal flash memory. (1) fentry (flash mode entry) bit (d3) the fentry bit controls entry to flash e/w enable mode. flash e/w enable mode can be entered only when fentry = 1. to set the fentry bit to 1, write a 0 and then a 1 to the fentry bit in succession while the fp pin = high. the fentry bit is cleared in the following cases: ? when the device is reset ? when a 0 is written to the fentry bit ? when the fp pin changes state from high to low 6.4.3 flash controle registers n flash controle register 1 (fcnt1) internal memory 6.4 registers associated with the internal flash memory
6 6-9 ver.0.10 when using a program in the flash memory while the fentry bit = 0, the ei vector entry is located at address h'0000 0080 of the flash memory. when running a flash rewrite program in ram while the fentry bit = 1, the ei vector entry is located at address h'0080 4000 of the ram, allowing for flash rewrite operation to be controlled using interrupts. table 6.4.1 changes of ei vector entry by fentry fentry ei vector entry address 0 flash memory area h'0000 0080 1 internal ram area h'0080 4000 (2) femmod (virtual flash emulation mode) bit (d7) the femmod bit controls entry to virtual flash emulation mode. virtual flash emulation mode is entered by setting the femmod bit to 1 while the fentry bit = 0. (for details, refer to section 6.7, "virtual flash emulation function.") internal memory 6.4 registers associated with the internal flash memory
6 6-10 ver.0.10 internal memory 6.4 registers associated with the internal flash memory n flash controle register 2 (fcnt2) d8 9 1011121314d15 fprot d bit name function r w 8 - 14 no functions assigned 0 15 fprot 0 : protection by lock bit effective (unlock) 1 : protection by lock bit not effective the flash control register 2 (fcnt2) controls invalidation of the internal flash memory protection by a lock bit (to disable erasing or programming of the flash memory). the flash memory protection becomes invalid (unlocked) by setting the fprot bit to 1, so that any blocks protected by the lock bit can be erased or programmed. to set the fprot bit to 1, write a 0 and then a 1 to the fprot bit in succession while the fentry bit = 1. the fprot bit is cleared to 0 by writing a 0 to the fprot bit and setting the fp pin low or the fentry bit to 0 immediately after reset. figure 6.4.2 protection unlocking flow fprot=0 yes no fentry=1 fprot=1 fprot is not set to 1 if write cycle to any other area occurs during this time fprot=0 fprot=1 fentry=1
6 6-11 ver.0.10 internal memory 6.4 registers associated with the internal flash memory n flash controle register 3 (fcnt3) d0123456d7 felevel d bit name function r w 0 - 6 no functions assigned 0 7 felevel 0 : normal level (raise erase margin) 1 : raise erase margin the flash control register 3 (fcnt3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. by setting the felevel bit to 1, the flash memory erase level can be deepened, which will result in an increased reliability margin.
6 6-12 ver.0.10 internal memory 6.4 registers associated with the internal flash memory n flash controle register 4 (fcnt4) d8 9 1011121314d15 freset d bit name function r w 8 - 14 no functions assigned 0 15 freset 0 : no operation performed (reset flash) 1 : reset the flash memory the flash control register 4 (fcnt4) controls canceling program/erase operation in the middle and initializing each status bit of flash status register 2 (fstat2). when the freset bit is set to 1, program/erase operation is canceled in the middle and each status bit of fstat2 is initialized (h'80). the freset bit is effective only when the fentry bit = 1. information on freset bit is ignored unless the fentry bit = 1. make sure that when programming or erasing the flash memory, the freset bit remains 0.
6 6-13 ver.0.10 figure 6.4.3 example for using the fcnt4 register internal memory 6.4 registers associated with the internal flash memory freset=1 yes no fentry=1 program/erase flash memory error found program/erase terminated normally freset=0 program/erase flash memory fentry=0
6 6-14 ver.0.10 6.4.4 virtual flash l bank registers n virtual flash l bank register 0 (felbank0) n virtual flash l bank register 1 (felbank1) n virtual flash l bank register 2 (felbank2) n virtual flash l bank register 3 (felbank3) internal memory 6.4 registers associated with the internal flash memory lbankad d01234567891011121314d15 d bit name function r w 0 modenl 0 : disable virtual flash function (virtual flash emulation enable) 1 : enable virtual flash function 1 - 7 no functions assigned 0 8 - 14 lbankad a12 - a18 of start address of the l bank (l bank address) to be selected 15 no functions assigned 0 note: this register must always be accessed in halfword. (1) modenl (virtual flash emulation enable) bit (d0) the modenl bit can be set to 1 after entering virtual flash emulation mode (by setting the femmod bit to 1 while the fentry bit = 0). this causes the virtual flash emulation function to become effective for the l bank area selected by the lbankad bits. (2) lbankad (l bank address) bits (d8-d14) the lbankad bits are provided for selecting one l bank from a total of 96 l banks separated every 8 kb. use these lbankad bits to set the seven bits, a12-a18, of the 32-bit start address of the l bank you want to select. (for details, refer to section 6.7, "virtual flash emulation function.") note: the m32170f4 and m32170f3 do not have virtual flash l bank register 3 (felbank3). mod enl
6 6-15 ver.0.10 6.4.5 virtual flash s bank registers n virtual flash s bank register 0 (fesbank0) n virtual flash s bank register 1 (fesbank1) internal memory 6.4 registers associated with the internal flash memory sbankad d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 d bit name function r w 0 modens 0 : disable virtual flash function (virtual flash emulation enable) 1 : enable virtual flash function 1 - 7 no functions assigned 0 8 - 15 sbankad a12 - a19 of start address of the s bank (s bank address) to be selected note: this register must always be accessed in halfword. (1) modens (virtual flash emulation enable) bit (d0) the modens bit can be set to 1 after entering virtual flash emulation mode (by setting the femmod bit to 1 while the fentry bit = 0). this causes the virtual flash emulation function to become effective for the s bank area selected by the sbankad bits. (2) sbankad (s bank address) bits (d8-d15) the sbankad bits are provided for selecting one s bank from a total of 192 s banks separated every 4 kb. use these sbankad bits to set the eight bits, a12-a19, of the 32-bit start address of the s bank you want to select. (for details, refer to section 6.7, "virtual flash emulation function.") mod ens
6 6-16 ver.0.10 6.5 programming of the internal flash memory 6.5.1 outline of programming flash memory when writing to the internal flash memory, there are following two methods to use depending on situation: (1) when the write program does not exist in the internal flash memory (2) when the write program already exists in the internal flash memory for (1), set the fp pin = high, mod0 = high, and mod1 = low to enter boot flash e/w enable mode. in this case, the reset vector entry is located at the beginning of the boot program area (h'8000 0000). (normally, the reset vector entry is located at the start address of the internal flash memory.) transfer the "flash write program" from the boot area into the internal ram using a boot program. after this transfer, jump to the ram and set the flash control register 1 fentry bit to 1 to make the flash memory ready for write. you now can write to the internal flash memory using the "flash write program" that has been transferred into the internal ram. for (2), set the fp pin = high, mod0 = low, and mod1 = low to enter flash e/w enable mode in single-chip mode. transfer the "flash write program" from the internal flash memory in which it has been prepared beforehand into the internal ram. after this transfer, jump to the ram and set the flash control register 1 (fcnt1) fentry bit to 1 using a program in the ram to make the flash memory ready for write. you now can write to the internal flash memory using the "flash write program" that has been transferred into the internal ram. or you can set the fp pin = high, mod0 = low, and mod1 = high to enter flash e/w enable mode in extended external mode. when in flash e/w enable mode (fp pin = 1, fentry bit = 1), the eit vector entry for external interrupt (ei) is moved to the beginning of the internal ram (h'0080 4000). during normal mode, the eit vector entry exists in the flash area (h'0000 0080). internal memory 6.5 programming of the internal flash memory
6 6-17 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.1 ei vector entry when in flash e/w enable mode ei vector entry internal rom area internal ram (h'0000 0080) h'0000 0000 h'00ff ffff h'0080 4000 internal rom area internal ram h'0080 3fff flash e/w enable mode (fentry=1) normal mode (fentry=0) h'0000 0000 h'0080 3fff ei vector entry (h'0080 4000) h'0080 4000 h'00ff ffff
6 6-18 ver.0.10 (1) when the write program does not exist in the internal flash memory use a program in the boot rom located on memory map to write to the flash memory. to transfer the write data, use serial i/o1 in clock-synchronized serial mode. use this serial transfer when writing to the flash memory using a flash programmer. internal memory 6.5 programming of the internal flash memory figure 6.5.2 procedure for writing to internal flash memory (when the write program does not exist in the flash memory) sio1 aaa aaa cpu aaa aaa sio1 aaa aaa cpu aaa a a a aaa flash write program aaaa aaaa mod1= l aaa aaa sio1 aaa a a a aaa cpu aaa a a a aaa aaa a a a aaa ram flash memory fp=l or h aaaa aaaa ram ram initial state (where the write program does not (exist in the flash memory) set the fp pin high, the mod0 pin high, and the mod1 pin low to place the device in boot mode + flash e/w enable mode. deassert reset and start up using the boot program. transfer the flash write program from boot rom to ram. jump to the flash write program in ram. using the flash write program in ram, set the flash control register 1 (fcnt1) fentry bit to 1. write data to the internal flash memory using the flash write program. when you finished writing, reset mod0 low and jump to the flash memory or apply reset to enter normal mode. m32r/e m32r/e m32r/e external device external device flash memory flash write data flash memory mod0=l boot rom boot rom boot rom mod1= l fp=h mod0=h mod1= l fp=h mod0=h reset=l reset=h reset=h flash write program write data write data external device write data
6 6-19 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.3 internal flash memory write timings (when the write program does not exist in the flash memory) reset mod0 fentry fp mod1 power on mode selected reset deasserted (boot program starts) mode selected reset deasserted writes to flash memory by boot program settings by boot program
6 6-20 ver.0.10 (2) when the write program already exists in the internal flash memory use the flash write program already stored in the internal flash memory to write to the flash memory. for write to the flash memory, use the internal peripheral circuits according to your programming system. (the data bus, serial i/o, and ports can be used.) the following shows an example for writing to the flash memory by using serial i/o0 in single-chip mode. internal memory 6.5 programming of the internal flash memory figure 6.5.4 procedure for writing to internal flash memory (when the write program already exists in the flash memory) sio0 aaa aaa cpu aaa aaa sio0 aaa aaa cpu aaa a a a aaa flash write program aaaa aaaa mod1= l aaa aaa sio0 aaa a a a aaa cpu aaa aaa aaa a a a aaa ram flash write program fp=l or h aaaa aaaa ram ram initial state (where the write program already exists in the flash memory) ordinary program in the flash memory is being executed. set the fp pin high, the mod1 pin low, and the mod0 pin low to place the device in single-chip + flash e/w enable mode. after determining the fp pin and mod1 pin levels, transfer the flash write program from the flash memory area into ram. jump to the flash write program in ram. using the flash write program in ram, set the flash control register 1 (fcnt1) fentry bit to 1. write data to the internal flash memory using the flash write program in ram. when you finished writing, jump to the program in the flash memory or apply reset to enter normal mode. m32r/e m32r/e m32r/e external device external device flash memory flash write data flash memory boot rom boot rom boot rom mod1= l fp=h mod1= l fp=h mod0=l mod0=l mod0=l flash write program write data write data external device write data
6 6-21 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.5 internal flash memory write timings (when the write program already exists in the flash memory) reset mod0 fentry fp "h" or "l" "h" or "l" (single-chip or extended external) mod1 "l" "h" or "l" write to flash memory by flash rewrite program flash rewrite starts flash mode turned off flash rewrite program transferred to ram flash mode turned on
6 6-22 ver.0.10 6.5.2 controlling operation mode during programming flash the device's operation modes are set by mod0, mod1, and flash control register 1 (fcnt1) fentry bit. the table below lists operation modes that may be set during flash write. table 6.5.1 operation modes set during flash write fp mod0 mod1 fentry (note) operation mode reset vector entry ei vector entry 0 0 0 single-chip mode start address of flash area 1000 flash memory (h'0000 0080) (h'0000 0000) 0 1 0 processor mode start address of external area external area (h'0000 0080) (h'0000 0000) 001 extended external mode start address of flash area 1010 flash memory (h'0000 0080) (h'0000 0000) 1001 single-chip mode start address of beginning of + flash e/w enable flash memory internal ram (h'0000 0000) (h'0080 4000) 1100 boot mode start address of flash area boot program area (h'0000 0080) (h'8000 0000) 1101 boot mode start address of beginning of + flash e/w enable boot program area internal ram (h'8000 0000) (h'0080 4000) 1011 extended external mode start address of beginning of + flash e/w enable flash memory internal ram (h'0000 0000) (h'0080 4000) 1 1 reserved note: indicates the fentry bit status of flash control register 1 (fcnt1). the bar "" denotes "don't care." (1) flash e/w enable mode flash e/w enable mode is a mode in which the internal flash memory can be programmed or erased. in flash e/w enable mode, no programs can be executed in the internal flash memory. therefore, before entering flash e/w enable mode, you need to transfer the necessary program into the internal ram and run the program in ram. internal memory 6.5 programming of the internal flash memory
6 6-23 ver.0.10 internal memory 6.5 programming of the internal flash memory (2) entering flash e/w enable mode flash e/w enable mode can be entered only when the device is operating in single-chip mode or extended external mode. namely, you can enter flash e/w enable mode only when the fp pin = high and the flash control register 1 (fcnt1) fentry bit = 1. you cannot enter flash e/w enable mode when the device is operating in processor mode or the fp pin = low. (3) detecting the mod0 and mod1 pin levels the mod0 and mod1 pin levels (high or low) can be verified using the p8 data register (port data register, h'00800 0708) mod0dt and mod1dt bits. n p8 data register (p8data) d0123456d7 mod0dt mod1dt p82dt p83dt p84dt p85dt p86dt p87dt d bit name function r w 0 mod0dt 0 : mod0 pin = low (mod0 data) 1 : mod0 pin = high 1 mod1dt 0 : mod1 pin = low (mod1 data) 1 : mod1 pin = high 2 p82dt depending on how the port direction register is set (port p82 data) ? when direction bit = 0 (input mode) 3 p83dt 0: port input pin = low (port p83 data) 1: port input pin = high 4 p84dt ? when direction bit = 1 (output mode) (port p84 data) 0: port output latch = low 5 p85dt 1: port output latch = high (port p85 data) 6 p86dt (port p86 data) 7 p87dt (port p87 data)
6 6-24 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.6 procedure for entering flash e/w enable mode note: for details about each command, refer to section 6.5.3, "programming procedure to internal flash memory." end start enter one of the following modes: ?single-chip mode + flash e/w enable mode ?boot mode + flash e/w enable mode ?extended external mode + flash e/w enable mode transfer e/w program to internal ram in each mode set flash control register in sfr area (fcnt1, h'0080 07e2) flash entry (fentry) bit to 0 set flash control register in sfr area (fcnt1, h'0080 07e2) flash entry (fentry) bit to 1 execute flash e/w command and various read commands (note) switched to flash e/w program 1 ? wait (by hardware timer or software timer) jump to flash memory or apply reset switched to normal mode mod0, 1 fp pin levels checked ok no end fmod(h'0080 07e0) fpmod p8data(h'0080 0708) d0=mod0dt d1=mod1dt
6 6-25 ver.0.10 internal memory 6.5 programming of the internal flash memory 6.5.3 programming procedure to the internal flash memory to write to the internal flash memory, set the device's operation mode to enter flash e/w enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal ram. in flash e/w enable mode, no data can be read out from the internal flash memory as in normal mode, so you cannot execute a program that exists in the internal flash memory. therefore, the flash write program must be prepared in the internal ram before entering flash e/w enable mode. (once you've entered flash e/w enable mode, you cannot use any command except flash commands to access the flash memory.) to access the internal flash memory in flash memory e/w enable mode, issue commands for the internal flash memory address to be operated on. the table below lists the commands that can be issued in flash memory e/w enable mode. note : during flash e/w enable mode, the flash memory cannot be accessed for read or write wordwise. table 6.5.2 commands in flash memory e/w enable mode command name issued command data read array command h'ffff page program command h'4141 lock bit program command h'7777 block erase command h'2020 erase all unlock block command h'a7a7 read status register command h'7070 clear status register command h'5050 read lock bit status command h'7171 verify command (note) h'd0d0 note: this command is used in conjunction with lock bit program, block erase, and erase all unlock block operations. (1) read array command read mode is entered by writing command data h'ffff to any address of the internal flash memory. then read the flash memory address you want to read out, and the content of that address will be read out. before exiting flash e/w enable mode, always be sure to execute the read array command.
6 6-26 ver.0.10 internal memory 6.5 programming of the internal flash memory (2) page program command flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses h'00 to h'ff). to write data to the flash memory (i.e., to program the flash memory), write the program command h'4141 to any address of the internal flash memory and then the program data to the address to which you want to write. with the page program command, you cannot write to the protected blocks. page program is automatically performed by the internal control circuit, and the completion of programming can be verified by checking the flash status register 1 (fstat1) fstat bit. (refer to section 6.4.2, "flash status registers.") while the fstat bit = 1, the next programming can not be performed. (3) lock bit program command flash memory can be protected against program/erase one block at a time. the lock bit program command is provided for protecting memory blocks. write the lock bit program command data h'7777 to any address of the internal flash memory. next, write the verify command data h'd0d0 to the last even address of the block you want to protect, and this memory block is protected against program/erase. to remove protection, disable lock bit-effectuated protection using the flash control register 2 (fcnt2) fprot bit (see section 6.4.3, "flash control registers") and erase the block whose protection you want to remove. (the content of this memory block is also erased.) the table below lists the target blocks and their specified addresses when writing the verify command data.
6 6-27 ver.0.10 internal memory 6.5 programming of the internal flash memory table 6.5.3 m32170f6 target blocks and specified addresses target block specified address 0 h'0000 3ffe 1 h'0000 5ffe 2 h'0000 7ffe 3 h'0000 fffe 4 h'0001 fffe 5 h'0002 fffe 6 h'0003 fffe 7 h'0004 fffe 8 h'0005 fffe 9 h'0006 fffe 10 h'0007 fffe 11 h'0008 fffe 12 h'0009 fffe 13 h'000a fffe 14 h'000b fffe table 6.5.4 m32170f4 target blocks and specified addresses target block specified address 0 h'0000 3ffe 1 h'0000 5ffe 2 h'0000 7ffe 3 h'0000 fffe 4 h'0001 fffe 5 h'0002 fffe 6 h'0003 fffe 7 h'0004 fffe 8 h'0005 fffe 9 h'0006 fffe 10 h'0007 fffe
6 6-28 ver.0.10 internal memory 6.5 programming of the internal flash memory table 6.5.5 m32170f3 target blocks and specified addresses target block specified address 0 h'0000 3ffe 1 h'0000 5ffe 2 h'0000 7ffe 3 h'0000 fffe 4 h'0001 fffe 5 h'0002 fffe 6 h'0003 fffe 7 h'0004 fffe 8 h'0005 fffe
6 6-29 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.7 block configuration of the m32170f6 flash memory m32170f6's internal flash memory area (768kb) h'0002 0000 8kb 16kb 8kb 32kb 64kb h'0000 0000 h'0000 7fff h'0000 8000 h'0001 ffff h'0000 3fff h'0000 4000 h'0000 ffff h'0001 0000 h'0000 5fff h'0000 6000 64kb h'0002 ffff 64kb h'0009 ffff h'0009 0000 64kb h'000a ffff h'000a 0000 64kb h'000b ffff h'000b 0000 64kb block 0 64kb 64kb 64kb 64kb 64kb h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff h'0006 0000 h'0006 ffff h'0007 0000 h'0007 ffff h'0008 0000 h'0008 ffff block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 uneven blocks even blocks block 9 block 10 block 11 block 12 block 13 block 14
6 6-30 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.8 block configuration of the m32170f4 flash memory m32170f4's internal flash memory area (512kb) h'0002 0000 8kb 16kb 8kb 32kb 64kb h'0000 0000 h'0000 7fff h'0000 8000 h'0001 ffff h'0000 3fff h'0000 4000 h'0000 ffff h'0001 0000 h'0000 5fff h'0000 6000 64kb h'0002 ffff 64kb 64kb 64kb block 0 64kb 64kb h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff h'0006 0000 h'0006 ffff h'0007 0000 h'0007 ffff block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 uneven blocks even blocks block 9 block 10
6 6-31 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.9 block configuration of the m32170f3 flash memory m32170f3's internal flash memory area (384kb) h'0002 0000 8kb 16kb 8kb 32kb 64kb h'0000 0000 h'0000 7fff h'0000 8000 h'0001 ffff h'0000 3fff h'0000 4000 h'0000 ffff h'0001 0000 h'0000 5fff h'0000 6000 64kb h'0002 ffff 64kb 64kb 64kb block 0 h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 uneven blocks even blocks
6 6-32 ver.0.10 internal memory 6.5 programming of the internal flash memory (4) block erase command the block erase command erases the contents of internal flash memory one block at a time. for block erase, write the command data h'2020 to any address of the internal flash memory. next, write the verify command data h'd0d0 to the last even address of the memory block you want to erase (see table 6.5.3, table 6.5.4, and table 6.5.5, "target blocks and specified addresses"). the content of this memory block is erased. with the block erase command, you cannot erase the protected blocks. block erase is automatically performed by the internal control circuit, and the completion of block erase can be verified by checking the flash status register 1 (fstat1) fstat bit. (refer to section 6.4.2, "flash status registers.") while the fstat bit = 1, you cannot erase the next block. (5) erase all unlock block command the erase all unlock block command erases all memory blocks that are not protected. to erase all unlock blocks, write the command data h'a7a7 to any address of the internal flash memory. next, write the command data h'd0d0 to any address of the internal flash memory, and all of unprotected memory blocks are erased. (6) read status register command the read status register command reads out the content of flash status register 2 (fstat2) that indicates whether flash memory write or erase operation has terminated normally or not. to read flash status register 2, write the command data h'7070 to any address of the internal flash memory. next, read any address of the internal flash memory, and the content of flash status register 2 (fstat2) is read out. (7) clear status register command the clear status register command clears the flash status register 2 (fstat2) d10, d11, and d12 bits to 0. write the command data h'5050 to any address of the internal flash memory, and flash status register 2 is cleared to 0. if an error occurs when programming or erasing the flash memory and the flash status register 2 (fstat2) erase (auto erase operating condition) or wrerr2 (program operating condition 2) bit is set to 1, you cannot perform the next program or erase operation unless wrerr1 (program operating condition 1) or wrerr2 (program operating condition 2) is cleared to 0.
6 6-33 ver.0.10 internal memory 6.5 programming of the internal flash memory flbst0 flbst1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 d bit name function r w 0 no functions assigned ? 1 flbst0 0 : protected (lock bit 0) 1 : not protected 2 - 8 no functions assigned ? 9 flbst1 0 : protected (lock bit 1) 1 : not protected (same content as flbst0 is output.) 10 - 15 no functions assigned ? the lock bit status register is a read-only register, which contains said lock bits independently for each block. (8) read lock bit status command the read lock bit status command allows you to check whether or not a memory block is protected against program/erase. write the command data h'7171 to any address of the internal flash memory. next, read the last even address of the block you want to check (see table 6.5.3, table 6.5.4, and table 6.5.5, "target blocks and specified addresses"), and the data you read shows whether or not the target block is protected. if the flbst0 (lock bit 0) bit and flbst1 (lock bit 1) bit of the data you read are 0s, it means that the target memory block is protected. if the flbst0 (lock bit 0) bit and flbst1 (lock bit 1) bit are 1s, it means that the target memory block is not protected. n lock bit status register (flbst)
6 6-34 ver.0.10 internal memory 6.5 programming of the internal flash memory follow the procedure described below to write to the lock bits. a) setting the lock bit to 0 (protect the block) issue the lock bit program command (h'7777) to the memory block you want to protect. b) setting the lock bit to 1 (unprotect the block) after setting the flash control register 2 fprot bit to invalidate lock bit-effectuated protection, use the block erase command (h'2020) or erase all unprotect block command (h'a7a7) to erase the memory block you want to unprotect. this is the only way to unprotect a memory block. you cannot set the lock bit alone to 1. c) status when the lock bit is reset the lock bit is unaffected by a reset or power outage because it is a nonvolatile bit. (9) execution flow of each command the diagrams below show an execution flow of each command. figure 6.5.10 read array start write read array command (h'ffff) to any address of internal flash memory read the internal flash memory address you want to read end
6 6-35 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.11 page program note 1: start writing from the beginning of a 256-byte boundary of the flash memory (lower address h'00). note 2: when program operation starts, you have the read status register command automatically entered. (you do not need to enter the read status register command until you issue another command.) note 3: examine the flash status register 2 erese (auto erase operating condition), wrerr1 (program operating condition 1), and wrerr2 (program operating condition 2) bits to check for program error. end write data to the internal flash memory address to which you want to write. (note 1) increment the previous write address by 2 and write the next data to the new address. write page program command (h'4141) to any address of internal flash memory. written to the internal flash memory by page program (note 2) programmed for one page ? no yes 1 s wait (by hardware timer or software timer) fstat bit = 1 yes no go to next page start read any address of internal flash memory to check for program error. (note 3) last address ? yes no time out ? 0.5s yes no forcibly terminated
6 6-36 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.12 lock bit program note 1: when program operation starts, you have the read status register command automatically entered. (you do not need to enter the read status register command until you issue another command.) note 2: examine the flash status register 2 erese (auto erase operating condition), wrerr1 (program operating condition 1), and wrerr2 (program operating condition 2) bits to check for program error. end write verify command (h'd0d0) to the last even address of the block you want to protect. written to the lock bit by program (note 1) write lock bit program command (h'7777) to any address of internal flash memory. 1 s wait (by hardware timer or software timer) fstat bit = 1 yes no start read any address of internal flash memory to check for program error. (note 2) time out ? 0.5s yes no forcibly terminated
6 6-37 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.13 block erase note 1: when erase operation starts, you have the read status register command automatically entered. (you do not need to enter the read status register command until you issue another command.) note 2: examine the flash status register 2 erese (auto erase operating condition), wrerr1 (program operating condition 1), and wrerr2 (program operating condition 2) bits to check for erase error. end write verify command (h'd0d0) to the last even address of the block you want to erase. flash memory contents erased by erase program (note 1) write erase command (h'2020) to any address of internal flash memory. 1 s wait (by hardware timer or software timer) fstat bit = 1 yes no start read any address of internal flash memory to check for erase error. (note 2) time out ? 1s yes no forcibly terminated
6 6-38 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.14 erase all unlock block note 1: when erase operation starts, you have the read status register command automatically entered. (you do not need to enter the read status register command until you issue another command.) note 2: examine the flash status register 2 erese (auto erase operating condition), wrerr1 (program operating condition 1), and wrerr2 (program operating condition 2) bits to check for erase error. end write verify command (h'd0d0) to any address in memory blocks you want to erase. flash memory contents erased by erase program (note 1) write erase all unlock block command (h'a7a7) to any address of internal flash memory. 1 s wait (by hardware timer or software timer) fstat bit = 1 yes no start read any address of internal flash memory to check for erase error. (note 2) time out ? 10s yes no forcibly terminated
6 6-39 ver.0.10 internal memory 6.5 programming of the internal flash memory figure 6.5.15 read status register figure 6.5.17 read lock bit status register figure 6.5.16 clear status register write read status command (h'7070) to any address of internal flash memory. start read any address of internal flash memory. end write clear status command (h'5050) to any address of internal flash memory. start end write read lock bit status command (h'7171) to any address of internal flash memory. start read the last even address of the block whose status you want to read. end
6 6-40 ver.0.10 internal memory 6.5 programming of the internal flash memory 6.5.4 flash write time (for reference) the time required for writing to the internal flash memory is shown below for your reference. (1) m32170f6 transfer time by sio (for a transfer data size of 768 kb) 1/57600 bps 1 (frame) 11 (number of transfer bits) 768 kb 150.2 [s] flash write time 768 kb/256-byte block 8 ms 24.6 [s] a erase time (entire area) 50 ms number of blocks = 750 [ms] ? total flash write time (entire 768 kb area) when communicating at 57600 bps using uart, the flash write time can be ignored because it is very short compared to the serial communication time. therefore, the flash write time can be calculated using the equation below: + a 151 [s] when writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: + a 25 [s] (2) m32170f4 transfer time by sio (for a transfer data size of 512 kb) 1/57600 bps 1 (frame) 11 (number of transfer bits) 512 kb 100.2 [s] flash write time 512 kb/256-byte block 8 ms 16.4 [s] a erase time (entire area) 50 ms number of blocks = 550 [ms] ? total flash write time (entire 512 kb area) when communicating at 57600 bps using uart, the flash write time can be ignored because it is very short compared to the serial communication time. therefore, the flash write time can be calculated using the equation below: + a 101 [s] when writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: + a 17 [s] . = . . = . . = . . = . . = . . = . . = . . = .
6 6-41 ver.0.10 internal memory 6.5 programming of the internal flash memory (3) m32170f3 transfer time by sio (for a transfer data size of 384 kb) 1/57600 bps 1 (frame) 11 (number of transfer bits) 384 kb 75.1 [s] flash write time 384 kb/256-byte block 8 ms 12.3 [s] a erase time (entire area) 50 ms number of blocks = 450 [ms] ? total flash write time (entire 384 kb area) when communicating at 57600 bps using uart, the flash write time can be ignored because it is very short compared to the serial communication time. therefore, the flash write time can be calculated using the equation below: + a 76 [s] when writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: + a 13 [s] . = . . = . . = . . = .
6 6-42 ver.0.10 internal memory 6.6 boot rom 6.6 boot rom the table below shows boot memory specifications of the 32170. table 6.6.1 boot memory specifications item specification capacity 8 kbytes location address h'8000 0000 - h'8000 1fff wait insertion operates with no wait states (with 40 mhz internal cpu memory clock) internal bus connection connected by 32-bit bus read can only be read when fp = 1, mod0 = 1, and mod1 = 0. when read in other modes, indeterminate values are read out. cannot be accessed for write. other because the boot rom area is a reserved area that can only be used in boot mode, the program cannot be modified.
6 6-43 ver.0.10 internal memory 6.7 virtual flash emulation function 6.7 virtual flash emulation function the 32170 has a special function, called the "virtual flash emulation function," which allows the internal ram to be mapped in blocks of 8 kbytes from the beginning (up to four blocks for the m32170f6, up to three blocks for the m32170f4 and m32170f3) into the internal flash memory area divided in units of 8 kbytes (l banks). similarly, this function allows the internal ram to be mapped in blocks of 4 kbytes, for the m32170f6 (up to two blocks) starting from the ram address h'0080 c000, for the m32170f4 and m32170f3 (up to two blocks) starting from the ram address h'0080 a000 into the internal flash memory area divided in units of 4 kbytes (s banks). when this function is used, the data placed in 8 kbyte or 4 kbyte blocks of internal ram can be moved to or from the l or s banks in the flash memory that are specified by the virtual flash bank register. for applications that require modifying data during program operation, this enables dynamic modification of data using 8 kbytes or 4 kbytes of ram areas. the ram blocks allocated for virtual flash emulation can be read or written to from both internal ram and internal flash memory areas. this function, when used in combination with the real-time debugger (rtd), permits you to look up or rewrite from outside the data tables created in the internal flash memory, thus facilitating data table tuning from an external device. before accessing the internal flash memory for programming, be sure to terminate this virtual flash emulation mode. figure 6.7.1 internal ram bank configuration of the m32170f6 ram bank l block 0 (felbank0) 8 kbytes h'0080 4000 h'0080 6000 h'0080 8000 h'0080 a000 h'0080 c000 h'0080 d000 ram bank l block 1 (felbank1) 8 kbytes ram bank l block 2 (felbank2) 8 kbytes ram bank l block 3 (felbank3) 8 kbytes ram bank s block 0 (fesbank0) 4 kbytes ram bank s block 1 (fesbank1) 4 kbytes
6 6-44 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.2 internal ram bank configuration of the m32170f4 and m3170f3 h'0080 4000 h'0080 6000 h'0080 8000 h'0080 a000 h'0080 b000 ram bank l block 0 (felbank0) 8 kbytes ram bank l block 1 (felbank1) 8 kbytes ram bank l block 2 (felbank2) 8 kbytes ram bank s block 0 (fesbank0) 4 kbytes ram bank s block 1 (fesbank1) 4 kbytes
6 6-45 ver.0.10 6.7.1 virtual flash emulation area the following shows the areas for which the virtual flash emulation function is effective. the virtual flash l bank registers (felbank0 to felbank3 for the m32170f6, felbank0 to felbank2 for the m32170f4 and m32170f3) allow one among all l banks of flash memory divided in 8 kbytes each to be selected by setting the seven bits a12-a18 of the start address of the desired l bank in the virtual flash l bank register lbankad bits. then, by setting the virtual flash l bank register modenl0-3 bits (for the m32170f6) or modenl0-2 bits (for the m32170f4 and m32170f3) to 1, the selected l bank area can be replaced with 8 kbyte blocks of internal ram from the beginning of the internal ram (up to four blocks for the m32170f6, or up to three blocks for the m32170f4 and m32170f3). similarly, the virtual flash s bank registers (fesbank0, fesbank1) allow one among all s banks of flash memory divided in 4 kbytes each to be selected by setting the eight bits a12-a19 of the start address of the desired s bank in the virtual flash s bank register sbankad bits. then, by setting the virtual flash s bank register modens0-1 bits to 1, the selected s bank area can be replaced with 4 kbyte blocks of internal ram in up to two blocks starting from h'0080 c000 for the m32170f6 or h'0080 a000 for the m32170f4 and m32170f3. for the m32170f6, you can choose four 8-kbyte l banks and two 4-kbyte s banks, for a total of six banks (maximum). for the m32170f4 and m32170f3, you can choose three 8-kbyte l banks and two 4-kbyte s banks, for a total of five banks (maximum). note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area (8 kbyte or 4 kbyte) selected according to the priority of virtual flash bank registers shown below is assigned. ? m32170f6 felbank0 > felbank1 > felbank2 > felbank3 > fesbank0 > fesbank1 ? m32170f4 and m32170f3 felbank0 > felbank1 > felbank2 > fesbank0 > fesbank1 note 2: during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. internal memory 6.7 virtual flash emulation function
6 6-46 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.3 the m32170f6's virtual flash emulation area divided in units of 8 kbytes figure 6.7.4 the m32170f6's virtual flash emulation area divided in units of 4 kbytes note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > felbank3 > fesbank0 > fesbank1 is assigned. note 2: when you access an 8-kbyte area (l bank) specified by virtual flash l bank registers 0-3, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > felbank3 > fesbank0 > fesbank1 is assigned. note 2: when you access an 4-kbyte area (s bank) specified by virtual flash s bank registers 0,1, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. h'0000 0000 h'0000 2000 h'0006 6000 h'0080 4000 h'0080 6000 l bank 0 (8 kbytes) h'0000 4000 h'0006 4000 8 kbytes h'000b e000 h'000b c000 h'0080 8000 h'0080 a000 l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 50 (8 kbytes) l bank 51 (8 kbytes) l bank 94 (8 kbytes) l bank 95 (8 kbytes) 8 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes h'0000 0000 h'0000 1000 h'0080 4000 h'0000 2000 h'000b f000 h'000b e000 h'0080 c000 h'0080 d000 s bank 0 (4 kbytes) s bank 1 (4 kbytes) s bank 2 (4 kbytes) s bank 190 (4 kbytes) s bank 191 (4 kbytes) 8 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes 8 kbytes
6 6-47 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.5 the m32170f4's virtual flash emulation area divided in units of 8 kbytes figure 6.7.6 the m32170f4's virtual flash emulation area divided in units of 4 kbytes note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > fesbank0 > fesbank1 is assigned. note 2: when you access an 8-kbyte area (l bank) specified by virtual flash l bank registers 0-2, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > fesbank0 > fesbank1 is assigned. note 2: when you access an 4-kbyte area (s bank) specified by virtual flash s bank registers 0,1, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. h'0000 0000 h'0000 2000 h'0080 4000 h'0080 6000 l bank 0 (8 kbytes) h'0000 4000 h'0007 e000 h'0007 c000 h'0080 8000 l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 62 (8 kbytes) l bank 63 (8 kbytes) 8 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes h'0000 0000 h'0000 1000 h'0080 4000 h'0000 2000 h'0007 f000 h'0007 e000 h'0080 a000 h'0080 b000 s bank 0 (4 kbytes) s bank 1 (4 kbytes) s bank 2 (4 kbytes) s bank 126 (4 kbytes) s bank 127 (4 kbytes) 8 kbytes 8 kbytes 4 kbytes 4 kbytes 8 kbytes
6 6-48 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.7 the m32170f3's virtual flash emulation area divided in units of 8 kbytes figure 6.7.8 the m32170f3's virtual flash emulation area divided in units of 4 kbytes note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > fesbank0 > fesbank1 is assigned. note 2: when you access an 8-kbyte area (l bank) specified by virtual flash l bank registers 0-2, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. note 1: if after setting the same bank area in multiple virtual flash bank registers, you enable the virtual flash emulation enable bit, the internal ram area selected in order of priority felbank0 > felbank1 > felbank2 > fesbank0 > fesbank1 is assigned. note 2: when you access an 4-kbyte area (s bank) specified by virtual flash s bank registers 0,1, its corresponding internal ram area is accessed. during virtual flash emulation mode, ram can be read or written to from both internal ram area and virtual flash setup area. h'0000 0000 h'0000 2000 h'0080 4000 h'0080 6000 l bank 0 (8 kbytes) h'0000 4000 h'0005 e000 h'0005 c000 h'0080 8000 l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 46 (8 kbytes) l bank 47 (8 kbytes) 8 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes h'0000 0000 h'0000 1000 h'0080 4000 h'0000 2000 h'0005 f000 h'0005 e000 h'0080 a000 h'0080 b000 s bank 0 (4 kbytes) s bank 1 (4 kbytes) s bank 2 (4 kbytes) s bank 94 (4 kbytes) s bank 95 (4 kbytes) 8 kbytes 8 kbytes 4 kbytes 4 kbytes 8 kbytes
6 6-49 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.9 values set in the m32170f6's virtual flash bank register when divided in units of 8 kbytes figure 6.7.10 values set in the m32170f6's virtual flash bank register when divided in units of 4 kbytes note: set the seven bits a12-a18 of the start address (32-bit) of each l bank of flash memory divided every 8 kbytes in the virtual flash l bank register's l bank address (lbankad) bits. note: set the eight bits a12-a19 of the start address (32-bit) of each s bank of flash memory divided every 4 kbytes in the virtual flash s bank register's s bank address (sbankad) bits. h'000 0 0000 l bank start address of bank in flash memory l bank address (lbankad) bit set value h'000 0 2000 h'000 0 4000 h'000 b c000 h'000 b e000 h'00 h'02 h'04 h'bc h'be (note) l bank 0 l bank 1 l bank 2 l bank 94 l bank 95 h'000 0 0000 s bank start address of bank in flash memory s bank address (sbankad) bit set value h'000 0 1000 h'000 0 2000 h'000 b e000 h'000 b f000 h'00 h'01 h'02 h'be h'bf (note) s bank 0 s bank 1 s bank 2 s bank 190 s bank 191
6 6-50 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.11 values set in the m32170f4's virtual flash bank register when divided in units of 8 kbytes figure 6.7.12 values set in the m32170f4's virtual flash bank register when divided in units of 4 kbytes note: set the seven bits a12-a18 of the start address (32-bit) of each l bank of flash memory divided every 8 kbytes in the virtual flash l bank register's l bank address (lbankad) bits. note: set the eight bits a12-a19 of the start address (32-bit) of each s bank of flash memory divided every 4 kbytes in the virtual flash s bank register's s bank address (sbankad) bits. h'000 0 0000 l bank start address of bank in flash memory l bank address (lbankad) bit set value h'000 0 2000 h'000 0 4000 h'000 7 c000 h'000 7 e000 h'00 h'02 h'04 h'7c h'7e (note) l bank 0 l bank 1 l bank 2 l bank 62 l bank 63 h'000 0 0000 s bank start address of bank in flash memory s bank address (sbankad) bit set value h'000 0 1000 h'000 0 2000 h'000 7 e000 h'000 7 f000 h'00 h'01 h'02 h'7e h'7f (note) s bank 0 s bank 1 s bank 2 s bank 126 s bank 127
6 6-51 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.13 values set in the m32170f3's virtual flash bank register when divided in units of 8 kbytes figure 6.7.14 values set in the m32170f3's virtual flash bank register when divided in units of 4 kbytes note: set the seven bits a12-a18 of the start address (32-bit) of each l bank of flash memory divided every 8 kbytes in the virtual flash l bank register's l bank address (lbankad) bits. note: set the eight bits a12-a19 of the start address (32-bit) of each s bank of flash memory divided every 4 kbytes in the virtual flash s bank register's s bank address (sbankad) bits. h'000 0 0000 l bank start address of bank in flash memory l bank address (lbankad) bit set value h'000 0 2000 h'000 0 4000 h'000 5 c000 h'000 5 e000 h'00 h'02 h'04 h'5c h'5e (note) l bank 0 l bank 1 l bank 2 l bank 46 l bank 47 h'000 0 0000 s bank start address of bank in flash memory s bank address (sbankad) bit set value h'000 0 1000 h'000 0 2000 h'000 5 e000 h'000 5 f000 h'00 h'01 h'02 h'5e h'5f (note) s bank 0 s bank 1 s bank 2 s bank 94 s bank 95
6 6-52 ver.0.10 internal memory 6.7 virtual flash emulation function 6.7.2 entering virtual flash emulation mode to enter virtual flash emulation mode, set the flash control register 1 (fcnt1) femmod bit to 1. after entering virtual flash emulation mode, set the virtual flash bank register moden bit to 1 to enable the virtual flash emulation function. in virtual flash emulation mode also, the internal ram area (h'0080 4000 through h'0080 dfff for the m32170f6, or h'8080 4000 through h'0080 bfff for the m32170f4 and m32170f3) can be accessed as internal ram. figure 6.7.15 virtual flash emulation mode sequence set ram location address in virtual flash bank register lbankadn address a12-a18 sbankadn address a12-a19 write flash data to ram enable virtual flash emulation function modenln 1 modensn 1 settings completed go to virtual flash emulation mode femmod 1 settings completed
6 6-53 ver.0.10 internal memory 6.7 virtual flash emulation function 6.7.3 application example of virtual flash emulation mode by locating two ram areas in the same virtual flash area using the virtual flash emulation function, you can rewrite data in the flash memory successively. figure 6.7.16 application example of virtual flash emulation (1/2) replace area flash ram block 0 data write to ram0 (1) operation when reset (2) program operation using ram block 0 initial value (3) program operation changed from ram block 0 to ram block 1 bank xx bank xx specified ram block 0 ram block 1 replace flash ram block 0 data write to ram1 initial value bank xx ram block 1 bank xx specified ram block 0 replace flash ram block 0 initial value bank xx ram block 1 ram block 1 bank xx specified (settings invalid)
6 6-54 ver.0.10 internal memory 6.7 virtual flash emulation function figure 6.7.17 application example of virtual flash emulation (2/2) (6) go to item (2) note : valid area (4) program operation using ram block 1 bank xx specified ram block 1 replace flash ram block 0 data write to ram0 initial value bank xx ram block 1 (5) program operation changed from ram block 1 to ram block 0 bank xx specified ram block 0 replace flash ram block 0 initial value bank xx ram block 1 ram block 1 bank xx specified (settings invalid)
6 6-55 ver.0.10 internal memory 6.8 connecting to a serial programmer 6.8 connecting to a serial programmer when you rewrite the internal flash memory using a general-purpose serial programmer in boot flash e/w enable mode, you need to process the pins on the 32170 shown below to make them suitable for the serial programmer. table 6.8.1 processing the 32170 pins when using a serial programmer pin name pin number function remark fp mod0 reset sclki1 rxd1 txd1 p84 vcce vcci vss 156 154 153 121 120 119 118 37,51,80,114,139,157, 205 98,125,137,171,195,225 17,22,24,38,52,81,99, 115,127,129,138,158, 172,196,206,226 osc-vcc 21 xout 20 xin 19 osc-vss 18 vref0 vref1 61 227 avcc0 avcc1 62 228 avss0 avss1 79 5 fvcc 128 vdd 170 transfer clock input serial data input (receive data) serial data output (transmit data) transmit/receive enable output flash memory protect operation mode 1 reset clock input clock output pll circuit power supply pll circuit ground pll circuit control input vcnt 23 a-d converter reference voltage input analog power supply analog ground flash memory power supply ram backup power supply 5 v power supply ground mod1 155 operation mode 0 need to be pulled high connect to ground connect to 3.3 v power supply connect to 5 v power supply note: all other pins do not need to be processed. p83 117 transmit/receive control need to be pulled high need to be pulled high need to be pulled high connect to ground connect to ground connect to 5 v power supply connect to 3.3 v power supply connect to 3.3 v power supply 3.3 v power supply
6 6-56 ver.0.10 internal memory 6.8 connecting to a serial programmer the diagram below shows an example of user system configuration which has had a serial programmer connected. after the user system is powered on, the serial programmer writes to the flash memory in clock-synchronized serial mode. no communication problems associated with the oscillation frequency may occur. if the system uses any 32170 pins which will connect to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. note that the serial programmer uses the addresses h'0000 0084 through h'0000 0093 as an area to check id for flash memory protection. figure 6.8.1 pin connection diagram note 1 : turn on the power to the user system before you write to the flash memory. note 2 : if the system circuit uses p83-p87, consideration must be taken for connection of a serial programmer. note 3 : p83 must have a high-level signal applied to it. note 4 : p64/sbi must be fixed high or low to ensure that interrupts will not be generated. note 5 : the pullup resistances of p83, p84, p86, and p87 must be set to suit system design conditions. note 6 : the typical pullup resistances of p83, p84, p86, and p87 are 4.7 to 10 k w . note 7 : all other ports, whether high or low, do not affect flash memory programming. aaa vref0, vref1 32170 vdd vcci avcc0, avcc1 osc-vcc vcce connects to 5 v power supply p85/txd1 p86/rxd1 p87/sclki1/sclko1 p84/sclki0/sclko0 connector various signals on flash programmer mod0 fp reset vss set microcomputer operating conditions xin xout vcnt avss0, avss1 oscvss to system circuit p83/rxd0 rxd (input) txd (output) sclko(output) busy (input) mod0 (output) fp (output) reset(output) gnd (output) 5v (input) user system circuit board fvcc mod1 connects to 3.3 v power supply
6 6-57 ver.0.10 6.9 precautions to be taken when rewriting flash memory the following describes precautions to be taken when you rewrite the flash memory using a general-purpose serial programmer in boot flash e/w enable mode. ? when you use the pins with the system that are used by a serial programmer, take measures not to affect the system when connecting a serial programmer. ? if the flash memory needs to be protected, set an appropriate id in the flash memory protect id verification area (h'0000 0084 through h'0000 0093). ? if the flash memory does not require protection, fill the entire flash memory protect id verification area (h'0000 0084 through h'0000 0093) with h'ff. internal memory 6.9 precautions to be taken when rewriting flash memory
6 6-58 ver.0.10 internal memory 6.9 precautions to be taken when rewriting flash memory ? this is a blank page. ?
chapter 7 chapter 7 reset 7.1 outline of reset 7.2 reset operation 7.3 internal state immediately after reset release 7.4 things to be considered after reset release
7 7-2 ver.0.10 7.1 outline of reset _____ the device is reset by applying a low-level signal to the reset input pin. the device is gotten out _____ of a reset state by releasing the reset input back high, upon which the reset vector entry address is set in the program counter (pc) and the program starts executing from the reset vector entry. 7.2 reset operation 7.2.1 reset at power-on _____ when powering on the device, hold the reset input low until its internal multiply-by-4 clock generator becomes oscillating stably. 7.2.2 reset during operation _____ to reset the device during operation, hold the reset input low for more than four clock periods of xin signal. 7.2.3 reset vector relocation during flash rewrite when placed in boot mode, the reset vector entry address is moved to the start address of the boot program space (address h'8000 0000). for details, refer to section 6.5, "programming of internal flash memory." reset 7.1 outline of reset
7 7-3 ver.0.10 reset 7.3 internal state immediately after reset release 7.3 internal state immediately after reset release the table below lists the register state of the device immediately after it has gotten out of reset. for details about the initial register state of each internal peripheral i/o, refer to each section in this manual where the relevant internal peripheral i/o is described. table 7.3.1 internal state immediately after reset register state after reset release psw (cr0) b'0000 0000 0000 0000 ??00 000? 0000 0000 (bsm, bie, bc bits = indeterminate) cbr (cr1) h'0000 0000 (c bit = 0) spi (cr2) indeterminate spu (cr3) indeterminate bpc (cr6) indeterminate pc h'0000 0000 (executed beginning with address h'0000 0000) (note) acc (accumulator) indeterminate note: when in boot mode, this changes to the start address of the boot program space (h'8000 0000).
7 7-4 ver.0.10 reset 7.4 things to be considered after reset release 7.4 things to be considered after reset release ? input/output ports after reset release, the 32170's input/output ports are disabled against input in order to prevent current from flowing through the port. to use any ports in input mode, enable them for input using the port input function enable register (pien) pien0 bit. for details, refer to section 8.3, "input/ output port related registers."
chapter 8 chapter 8 input/output ports and pin functions 8.1 outline of input/output ports 8.2 selecting pin functions 8.3 input/output port related registers 8.4 port peripheral circuits
8 8-2 ver.0.10 8.1 outline of input/output ports the 32170 has a total of 157 input/output ports from p0 to p22 (of which p5 is reserved for future use, however). these input/output ports can be set for input or output mode by a direction register. each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral i/o or extended external bus signal line. pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's operation mode register. (if any internal peripheral i/o has still another function, you need to set the register provided for that peripheral i/o.) as a new function, the 32170 internally contains a port input function enable bit that can be used to prevent current from flowing into the input ports. this helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite. to use any ports in input mode, you need to set the port input function enable bit accordingly. the input/output ports are outlined in the next pages. input/output ports and pin functions 8.1 outline of input/output ports
8 8-3 ver.0.10 input/output ports and pin functions 8.1 outline of input/output ports table 8.1.1 outline of input/output ports item specification number of ports total 157 lines p0 : p00 - p07 (8 lines) p1 : p10 - p17 (8 lines) p2 : p20 - p27 (8 lines) p3 : p30 - p37 (8 lines) p4 : p41 - p47 (7 lines) p6 : p61 - p67 (7 lines) p7 : p70 - p77 (8 lines) p8 : p82 - p87 (6 lines) p9 : p93 - p97 (5 lines) p10 : p100 - p107 (8 lines) p11 : p110 - p117 (8 lines) p12 : p124 - p127 (4 lines) p13 : p130 - p137 (8 lines) p14 : p140 - p147 (8 lines) p15 : p150 - p157 (8 lines) p16 : p160 - p167 (8 lines) p17 : p172 - p177 (6 lines) p18 : p180 - p187 (8 lines) p19 : p190 - p197 (8 lines) p20 : p200 - p203 (4 lines) p21 : p210 - p217 (8 lines) p22 : p220 - p225 (6 lines) port function the input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (however, p64 is an ___ sbi input-only port and p221 is a can input-only port.) pin function shared with peripheral i/o or extended external signals to serve dual functions (or with two or more peripheral i/o functions to serve multiple functions) pin function switchover p0 - p4, p224, p225 : depends on cpu operation mode (determined by setting mod0 and mod1 pins) p6 - p22 : as set by each input/output port's operation mode register (however, peripheral i/o pin functions are selected by peripheral i/o registers.)
8 8-4 ver.0.10 input/output ports and pin functions 8.2 selecting pin functions 8.2 selecting pin functions each input/output port serves dual functions sharing the pin with other internal peripheral i/o or extended external bus signal line (or triple functions sharing the pin with two or more peripheral i/o functions). pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's operation mode register. p0-p4, p224, and p225, when the cpu is set to operate in extended external mode or processor mode, all are switched to serve as signal pins for external access. the cpu operation mode is determined by setting the mod0 and mod1 pins (see the table below). table 8.2.1 cpu operation mode and pin functions of p0-p4, p224, and p225 mod0 mod1 operation mode pin functions of p0-p4, p224, and p225 vss vss single-chip mode input/output port pin vss vcce extended external mode extended external signal pin vcce vss processor mode vcce vcce reserved (use inhibited) note: vcce and vss are connected to +5 v and gnd, respectively. p6-p22 (except p64, p221, p224, and p225) have their pin functions switched between input/ output port pins and internal peripheral i/o pins by setting each port's operation mode register. if any internal peripheral i/o has multiple pin functions, you need to set the register provided for that peripheral i/o to select the desired pin function. note that settings of fp pin and mod1 pin during internal flash memory write operation do not affect the pin functions.
8 8-5 ver.0.10 input/output ports and pin functions 8.2 selecting pin functions figure 8.2.1 input/output ports and pin function assignments note 1: pin functions are switched over by setting mod0 and mod1 pins. note 2: pin functions are switched over by setting mod0 and mod1 pins. also, use of this pin requires caution because it has a debug event function. p0 p1 p2 p3 p4 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p5 db0 012 3456 7 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 a23 a24 a25 a26 a27 a28 a29 a30 a15 a16 a17 a18 a19 a20 a21 a22 blw/ ble bhw/ bhe rd cs0 cs1 a13 a14 (p61) (p62) (p63) sbi sclki4/ sclko4 adtrg bclk/ wr wait hreq hack rtdtxd rtdrxd rtdack rtdclk txd0 rxd0 sclki0/ sclko0 txd1 rxd1 sclki1/ sclko1 to16 to17 to18 to19 to20 to11 to12 to13 to14 to15 to10 to9 to8 to3 to4 to5 to6 to7 to2 to1 to0 tclk0 tclk1 tclk2 tclk3 tin16 tin17 tin18 tin19 tin20 tin21 tin22 tin23 tin8 tin9 tin10 tin11 tin12 tin13 tin14 tin15 tin0 tin1 tin2 tin3 tin4 tin5 tin6 tin7 settings of cpu operation mode (note 1) (reserved) settings of input/ output port operation mode register p16 to21 to22 to23 to24 to25 to26 to27 to28 p17 tin24 tin25 txd2 rxd2 txd3 rxd3 p18 p19 to29 to30 to31 to32 to33 to34 to35 to36 p20 txd4 rxd4 rxd5 p21 to37 to38 to39 to40 to41 to42 to43 to44 p22 ctx crx (p222) (p223) a11 (note 2) a12 (note 2) tin26 tin27 tin28 tin29 tin30 tin31 tin32 tin33 txd5 sclki5/ sclko5
8 8-6 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers 8.3 input/output port related registers included in the 32170 as input/output port related registers are the port data registers, port direction registers, and port operation mode registers. of these, the port operation mode registers are provided for only p6-p22. ports p0-p4, p224, and p225 have their pin functions determined by setting the cpu operation mode (fp, mod0, and mod1 pins). port p5 is reserved for future use. the tables below show an input/output port related register map. figure 8.3.1 input/output port related register map (1/2) address d0 d7 +0 address d8 d15 blank addresses are reserved. p1 data register (p1data) p3 data register (p3data) p7 data register (p7data) p9 data register (p9data) p11 data register (p11data) p13 data register (p13data) p15 data register (p15data) p1 direction register (p1dir) p3 direction register (p3dir) p7 direction register (p7dir) p9 direction register (p9dir) p11 direction register (p11dir) p17 data register (p17data) p19 data register (p19data) p21 data register (p21data) p13 direction register (p13dir) p15 direction register (p15dir) p17 direction register (p17dir) p19 direction register (p19dir) p21 direction register (p21dir) h'0080 0700 h'0080 0702 h'0080 0704 h'0080 0706 h'0080 0708 h'0080 070a h'0080 070c h'0080 070e h'0080 0720 h'0080 0722 h'0080 0724 h'0080 0726 h'0080 0728 h'0080 072a h'0080 072c h'0080 072e h'0080 0710 h'0080 0730 h'0080 0712 h'0080 0714 h'0080 0716 h'0080 0732 h'0080 0734 h'0080 0736 p0 data register (p0data) p2 data register (p2data) p4 data register (p4data) p6 data register (p6data) p8 data register (p8data) p10 data register (p10data) p12 data register (p12data) p14 data register (p14data) p0 direction register (p0dir) p2 direction register (p2dir) p4 direction register (p4dir) p6 direction register (p6dir) p8 direction register (p8dir) p10 direction register (p10dir) p16 data register (p16data) p18 data register (p18data) p20 data register (p20data) p22 data register (p22data) p12 direction register (p12dir) p14 direction register (p14dir) p16 direction register (p16dir) p18 direction register (p18dir) p20 direction register (p20dir) p22 direction register (p22dir) +1 address
8 8-7 ver.0.10 8.3.2 input/output port related register map (2/2) input/output ports and pin functions 8.3 input/output port related registers p7 operation mode register (p7mod) p9 operation mode register (p9mod) p11 operation mode register (p11mod) p13 operation mode register (p13mod) p15 operation mode register (p15mod) p17 operation mode register (p17mod) port input function enable register (pien) p19 operation mode register (p19mod) p21 operation mode register (p21mod) p6 operation mode register (p6mod) p8 operation mode register (p8mod) p10 operation mode register (p10mod) p12 operation mode register (p12mod) p14 operation mode register (p14mod) p16 operation mode register (p16mod) p18 operation mode register (p18mod) p20 operation mode register (p20mod) p22 operation mode register (p22mod) h'0080 0746 h'0080 0748 h'0080 074a h'0080 074c h'0080 074e h'0080 0750 h'0080 0744 h'0080 0752 h'0080 0754 h'0080 0756 blank addresses are reserved. address d0 d7 +0 address d8 d15 +1 address
8 8-8 ver.0.10 8.3.1 port data registers n p0 data register (p0data) n p1 data register (p1data) n p2 data register (p2data) n p3 data register (p3data) n p4 data register (p4data) n p6 data register (p6data) n p7 data register (p7data) n p8 data register (p8data) n p9 data register (p9data) n p10 data register (p10data) n p11 data register (p11data) n p12 data register (p12data) n p13 data register (p13data) n p14 data register (p14data) n p15 data register (p15data) n p16 data register (p16data) n p17 data register (p17data) n p18 data register (p18data) n p19 data register (p19data) n p20 data register (p20data) n p21 data register (p21data) n p22 data register (p22data) input/output ports and pin functions 8.3 input/output port related registers d0123456d7 ( d8 9 10 11 12 13 14 d15 ) pn0dt pn1dt pn2dt pn3dt pn4dt pn5dt pn6dt pn7dt note: n = 0 to 22 (except for p5)
8 8-9 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers d bit name function r w 0 pn0dt (port pn0 data) depending on how the port direction register is set 1 pn1dt (port pn1 data) ? when direction bit = 0 (input mode) 2 pn2dt (port pn2 data) 0: port input pin = low 3 pn3dt (port pn3 data) 1: port input pin = high 4 pn4dt (port pn4 data) ? when direction bit = 1 (output mode) 5 pn5dt (port pn5 data) 0: port output latch = low 6 pn6dt (port pn6 data) 1: port output latch = high 7 pn7dt (port pn7 data) note 1: the following bits have no functions assigned (when read, the bit = 0; writing to the bit has no effect). note 2: port p64 is input mode-only. writing to the p64dt bit has no effect. note 3: port p221 is input mode-only. writing to the p221dt bit has no effect. note 4: ports p80 and p81 are input mode-only. writing to the p80dt and p81dt bits has no effect. when read out, p80 shows the mod0 pin level and p81 shows the mod1 pin level. the p80dt and p81dt bits are write-protected.
8 8-10 ver.0.10 8.3.2 port direction registers n p0 direction register (p0dir) n p1 direction register (p1dir) n p2 direction register (p2dir) n p3 direction register (p3dir) n p4 direction register (p4dir) n p6 direction register (p6dir) n p7 direction register (p7dir) n p8 direction register (p8dir) n p9 direction register (p9dir) n p10 direction register (p10dir) n p11 direction register (p11dir) n p12 direction register (p12dir) n p13 direction register (p13dir) n p14 direction register (p14dir) n p15 direction register (p15dir) n p16 direction register (p16dir) n p17 direction register (p17dir) n p18 direction register (p18dir) n p19 direction register (p19dir) n p20 direction register (p20dir) n p21 direction register (p21dir) n p22 direction register (p22dir) input/output ports and pin functions 8.3 input/output port related registers d0123456d7 ( d8 9 10 11 12 13 14 d15 ) pn0dir pn1dir pn2dir pn3dir pn4dir pn5dir pn6dir pn7dir note: n = 0 to 22 (except for p5)
8 8-11 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers d bit name function r w 0 pn0dir (port pn0 direction bit) 0: input mode (when reset) 1 pn1dir (port pn1 direction bit) 1: output mode 2 pn2dir (port pn2 direction bit) 3 pn3dir (port pn3 direction bit) 4 pn4dir (port pn4 direction bit) 5 pn5dir (port pn5 direction bit) 6 pn6dir (port pn6 direction bit) 7 pn7dir (port pn7 direction bit) note 1: the following bits have no functions assigned (when read, the bit = 0; writing to the bit has no effect). note 2: when reset, all ports are placed in input mode. note 3: port p64 is input mode-only. the register does not have a p64dir bit. note 4: ports p80 and p81 are input mode-only. the register does not have p80dir and p81dir bits. note 5: port p221 is input mode-only. the register does not have a p221dir bit.
8 8-12 ver.0.10 8.3.3 port operation mode registers n p6 operation mode register (p6mod) input/output ports and pin functions 8.3 input/output port related registers d0123456d7 p65mod p66mod p67mod d bit name function r w 0 - 4 no functions assigned 0 5 p65mod 0 : p65 (port p65 operation mode) 1 : sclki4 / sclko4 6 p66mod 0 : p66 (port p66 operation mode) 1 : sclki5 / sclko5 7 p67mod 0 : p67 (port p67 operation mode) _____ 1 : adtrg note 1: port 60 is not accommodated. note 2: ports p61-p63 are always input/output ports (single-function pins). ___ note 3: port p64 is an sbi input-only pin. the pin level can be verified by reading the p64 data register.
8 8-13 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p7 operation mode register (p7mod) d8 9 1011121314d15 p70mod p71mod p72mod p73mod p74mod p75mod p76mod p77mod d bit name function r w 8 p70mod 0 : p70 (port p70 operation mode) __ 1 : bclk / wr 9 p71mod 0 : p71 (port p71 operation mode) ____ 1 : wait 10 p72mod 0 : p72 (port p72 operation mode) ____ 1 : hreq 11 p73mod 0 : p73 (port p73 operation mode) ____ 1 : hack 12 p74mod 0 : p74 (port p74 operation mode) 1 : rtdtxd 13 p75mod 0 : p75 (port p75 operation mode) 1 : rtdrxd 14 p76mod 0 : p76 (port p76 operation mode) 1 : rtdack 15 p77mod 0 : p77 (port p77 operation mode) 1 : rtdclk
8 8-14 ver.0.10 n p8 operation mode register (p8mod) input/output ports and pin functions 8.3 input/output port related registers d0123456d7 p82mod p83mod p84mod p85mod p86mod p87mod d bit name function r w 0, 1 no functions assigned 0 2 p82mod 0 : p82 (port p82 operation mode) 1 : txd0 3 p83mod 0 : p83 (port p83 operation mode) 1 : rxd0 4 p84mod 0 : p84 (port p84 operation mode) 1 : sclki0 / sclko0 5 p85mod 0 : p85 (port p85 operation mode) 1 : txd1 6 p86mod 0 : p86 (port p86 operation mode) 1 : rxd1 7 p87mod 0 : p87 (port p87 operation mode) 1 : sclki1 / sclko1 note : ports p80 and p81 are not accommodated.
8 8-15 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p9 operation mode register (p9mod) d8 9 1011121314d15 p93mod p94mod p95mod p96mod p97mod d bit name function r w 8 - 10 no functions assigned 0 11 p93mod 0 : p93 (port p93 operation mode) 1 : to16 12 p94mod 0 : p94 (port p94 operation mode) 1 : to17 13 p95mod 0 : p95 (port p95 operation mode) 1 : to18 14 p96mod 0 : p96 (port p96 operation mode) 1 : to19 15 p97mod 0 : p97 (port p97 operation mode) 1 : to20 note : ports p90 - p92 are not accommodated.
8 8-16 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p10 operation mode register (p10mod) d0123456d7 p100mod p101mod p102mod p103mod p104mod p105mod p106mod p107mod d bit name function r w 0 p100mod 0 : p100 (port p100 operation mode) 1 : to8 1 p101mod 0 : p101 (port p101 operation mode) 1 : to9 2 p102mod 0 : p102 (port p102 operation mode) 1 : to10 3 p103mod 0 : p103 (port p103 operation mode) 1 : to11 4 p104mod 0 : p104 (port p104 operation mode) 1 : to12 5 p105mod 0 : p105 (port p105 operation mode) 1 : to13 6 p106mod 0 : p106 (port p106 operation mode) 1 : to14 7 p107mod 0 : p107 (port p107 operation mode) 1 : to15
8 8-17 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p11 operation mode register (p11mod) d8 9 1011121314d15 p110mod p111mod p112mod p113mod p114mod p115mod p116mod p117mod d bit name function r w 8 p110mod 0 : p110 (port p110 operation mode) 1 : to0 9 p111mod 0 : p111 (port p111 operation mode) 1 : to1 10 p112mod 0 : p112 (port p112 operation mode) 1 : to2 11 p113mod 0 : p113 (port p113 operation mode) 1 : to3 12 p114mod 0 : p114 (port p114 operation mode) 1 : to4 13 p115mod 0 : p115 (port p115 operation mode) 1 : to5 14 p116mod 0 : p116 (port p116 operation mode) 1 : to6 15 p117mod 0 : p117 (port p117 operation mode) 1 : to7
8 8-18 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p12 operation mode register (p12mod) d0123456d7 p124mod p125mod p126mod p127mod d bit name function r w 0 - 3 no functions assigned 0 4 p124mod 0 : p124 (port p124 operation mode) 1 : tclk0 5 p125mod 0 : p125 (port p125 operation mode) 1 : tclk1 6 p126mod 0 : p126 (port p126 operation mode) 1 : tclk2 7 p127mod 0 : p127 (port p127 operation mode) 1 : tclk3 note : ports p120 - p123 are not accommodated.
8 8-19 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p13 operation mode register (p13mod) d8 9 1011121314d15 p130mod p131mod p132mod p133mod p134mod p135mod p136mod p137mod d bit name function r w 8 p130mod 0 : p130 (port p130 operation mode) 1 : tin16 9 p131mod 0 : p131 (port p131 operation mode) 1 : tin17 10 p132mod 0 : p132 (port p132 operation mode) 1 : tin18 11 p133mod 0 : p133 (port p133 operation mode) 1 : tin19 12 p134mod 0 : p134 (port p134 operation mode) 1 : tin20 13 p135mod 0 : p135 (port p135 operation mode) 1 : tin21 14 p136mod 0 : p136 (port p136 operation mode) 1 : tin22 15 p137mod 0 : p137 (port p137 operation mode) 1 : tin23
8 8-20 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p14 operation mode register (p14mod) d0123456d7 p140mod p141mod p142mod p143mod p144mod p145mod p146mod p147mod d bit name function r w 0 p140mod 0 : p140 (port p140 operation mode) 1 : tin8 1 p141mod 0 : p141 (port p141 operation mode) 1 : tin9 2 p142mod 0 : p142 (port p142 operation mode) 1 : tin10 3 p143mod 0 : p143 (port p143 operation mode) 1 : tin11 4 p144mod 0 : p144 (port p144 operation mode) 1 : tin12 5 p145mod 0 : p145 (port p145 operation mode) 1 : ttin13 6 p146mod 0 : p146 (port p146 operation mode) 1 : tin14 7 p147mod 0 : p147 (port p147 operation mode) 1 : tin15
8 8-21 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p15 operation mode register (p15mod) d8 9 1011121314d15 p150mod p151mod p152mod p153mod p154mod p155mod p156mod p157mod d bit name function r w 8 p150mod 0 : p150 (port p150 operation mode) 1 : tin0 9 p151mod 0 : p151 (port p151 operation mode) 1 : tin1 10 p152mod 0 : p152 (port p152 operation mode) 1 : tin2 11 p153mod 0 : p153 (port p153 operation mode) 1 : tin3 12 p154mod 0 : p154 (port p154 operation mode) 1 : tin4 13 p155mod 0 : p155 (port p155 operation mode) 1 : tin5 14 p156mod 0 : p156 (port p156 operation mode) 1 : tin6 15 p157mod 0 : p157 (port p157 operation mode) 1 : tin7
8 8-22 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p16 operation mode register (p16mod) d0123456d7 p160mod p161mod p162mod p163mod p164mod p165mod p166mod p167mod d bit name function r w 0 p160mod 0 : p160 (port p160 operation mode) 1 : to21 1 p161mod 0 : p161 (port p161 operation mode) 1 : to22 2 p162mod 0 : p162 (port p162 operation mode) 1 : to23 3 p163mod 0 : p163 (port p163 operation mode) 1 : to24 4 p164mod 0 : p164 (port p164 operation mode) 1 : to25 5 p165mod 0 : p165 (port p165 operation mode) 1 : to26 6 p166mod 0 : p166 (port p166 operation mode) 1 : to27 7 p167mod 0 : p167 (port p167 operation mode) 1 : to28
8 8-23 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p17 operation mode register (p17mod) d8 9 1011121314d15 p172mod p173mod p174mod p175mod p176mod p177mod d bit name function r w 8, 9 no functions assigned 0 10 p172mod 0 : p172 (port p172 operation mode) 1 : tin24 11 p173mod 0 : p173 (port p173 operation mode) 1 : tin25 12 p174mod 0 : p174 (port p174 operation mode) 1 : txd2 13 p175mod 0 : p175 (port p175 operation mode) 1 : rxd2 14 p176mod 0 : p176 (port p176 operation mode) 1 : txd3 15 p177mod 0 : p177 (port p177 operation mode) 1 : rxd3 note : ports p170 and p171 are not accommodated.
8 8-24 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p18 operation mode register (p18mod) d0123456d7 p180mod p181mod p182mod p183mod p184mod p185mod p186mod p187mod d bit name function r w 0 p180mod 0 : p180 (port p180 operation mode) 1 : to29 1 p181mod 0 : p181 (port p181 operation mode) 1 : to30 2 p182mod 0 : p182 (port p182 operation mode) 1 : to31 3 p183mod 0 : p183 (port p183 operation mode) 1 : to32 4 p184mod 0 : p184 (port p184 operation mode) 1 : to33 5 p185mod 0 : p185 (port p185 operation mode) 1 : to34 6 p186mod 0 : p186 (port p186 operation mode) 1 : to35 7 p187mod 0 : p187 (port p187 operation mode) 1 : to36
8 8-25 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p19 operation mode register (p19mod) d8 9 1011121314d15 p190mod p191mod p192mod p193mod p194mod p195mod p196mod p197mod d bit name function r w 8 p190mod 0 : p190 (port p190 operation mode) 1 : tin26 9 p191mod 0 : p191 (port p191 operation mode) 1 : tin27 10 p192mod 0 : p192 (port p192 operation mode) 1 : tin28 11 p193mod 0 : p193 (port p193 operation mode) 1 : tin29 12 p194mod 0 : p194 (port p194 operation mode) 1 : tin30 13 p195mod 0 : p195 (port p195 operation mode) 1 : tin31 14 p196mod 0 : p196 (port p196 operation mode) 1 : tin32 15 p197mod 0 : p197 (port p197 operation mode) 1 : tin33
8 8-26 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p20 operation mode register (p20mod) d0123456d7 p200mod p201mod p202mod p203mod d bit name function r w 0 p200mod 0 : p200 (port p200 operation mode) 1 :txd4 1 p201mod 0 : p201 (port p201 operation mode) 1 : rxd4 2 p202mod 0 : p202 (port p202 operation mode) 1 : txd5 3 p203mod 0 : p203 (port p203 operation mode) 1 : rxd5 4 - 7 no functions assigned 0 note : ports p204 - p207 are not accommodated.
8 8-27 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p21 operation mode register (p21mod) d8 9 1011121314d15 p210mod p211mod p212mod p213mod p214mod p215mod p216mod p217mod d bit name function r w 8 p210mod 0 : p210 (port p210 operation mode) 1 : to37 9 p211mod 0 : p211 (port p211 operation mode) 1 : to38 10 p212mod 0 : p212 (port p212 operation mode) 1 : to39 11 p213mod 0 : p213 (port p213 operation mode) 1 : to40 12 p214mod 0 : p214 (port p214 operation mode) 1 : to41 13 p215mod 0 : p215 (port p215 operation mode) 1 : to42 14 p216mod 0 : p216 (port p216 operation mode) 1 : to43 15 p217mod 0 : p217 (port p217 operation mode) 1 : to44
8 8-28 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n p22 operation mode register (p22mod) d0123456d7 p220mod p224mod p225mod d bit name function r w 0 p220mod 0 : p220 (port p220 operation mode) 1 : ctx 1 - 3 no functions assigned 0 4 p224mod 0 : p224 (port p224 operation mode) 1 : use inhibited 5 p225mod 0 : p225 (port p225 operation mode) 1 : use inhibited 6 - 7 no functions assigned 0 note 1: p221 is a can input-only pin. note 2: p222-p223 are always input/output ports (single-function pins). note 3: p224 and p225 have their pin functions changed depending on how the mod0 and mod1 pins are set. also, use of these ports requires caution because they have a debug event function. note 4: p226 and p227 are not accommodated.
8 8-29 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers n port input function enable register (pien) d8 9 1011121314d15 pien0 d bit name function r w 8 - 14 no functions assigned 0 15 pien0 0 : disables input (to prevent current from flowing in) (port input function enable bit) 1 : enables input this register is provided to prevent current from flowing into the port input pin. because after reset this register is set to disable input, it must be set to 1 before input can be processed. during boot mode, all pins shared with serial i/o function are enabled for input, so that when rewriting the flash memory via serial communication, you can set this register to 0 to prevent current from flowing in from any pins other than serial i/o function. the next page lists the pins that can be controlled by the port input function enable register in each mode.
8 8-30 ver.0.10 input/output ports and pin functions 8.3 input/output port related registers mode name controllable pins noncontrollable pins p00 - p07, p10 - p17, p20 - p27 p64, p221, fp p30 -p37 , p41 - p47, p61 - p63 single chip p65 - p67, p70 - p77, p82 - p87 p93 - p97, p100 - p107, p110 - p117 p124 - p127, p130 - p137, p140 - p147 p150 - p157, p160 - p167, p172 - p177 p180 - p187, p190 - p197, p200 - p203 p210 - p217, p220, p222 - p225 p61 - p63, p65 - p67, p70 - p77 p00 - p07, p10 - p17 p82 - p87, p93 -p97, p100 - p107 p20 - p27, p30 - p37 extended external p110 - p117, p124 - p127, p130 - p137 p41 - p47, p64, p221, p224 microprocessor p140 - p147, p150 - p157, p160 - p167 p225, fp p172 - p177, p180 - p187, p190 - p197 p200 - p203, p210 - p217, p220 p222 - p223 p00 - p07, p10 - p17, p20 - p27 p64, p66, p82 - p87 p30 -p37 , p41 - p47, p61 - p63 p174 - p177, p200 - p203 boot (single chip) p67, p70 - p77, p93 - p97 p221, fp p100 - p107, p110 - p117, p124 - p127 p130 - p137, p140 - p147, p150 - p157 p160 - p167, p172 - p173, p180 - p187 p190 - p197, p210 - p217, p220 p222 - p225
8 8-31 ver.0.10 input/output ports and pin functions 8.4 port peripheral circuits 8.4 port peripheral circuits figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. figure 8.4.1 port peripheral circuit diagram (1) note 2: denotes pins. note 1: ports p00-p07, p10-p17, p20-p27, p30-p37, p41-p47, and p224-p225 when operating in extended external mode or processor mode, function as external bus interface control signals, but their functional description in this block diagram is omitted. p00 - p07 (db0-db7) p10 - p17 (db8-db15) p20 - p27 (a23-a30) p30 - p37 (a15-a22) ___ ___ p41 (blw / ble) ___ ___ p42 (bhw / bhe) __ p43 (rd) ___ p44 (cs0) ___ p45 (cs1) p46 - p47 (a13-a14) p61 - p63 p224 - p225 (a11-a12) p222 - p223 _____ p67 (adtrg) p75 (rtdrxd) p77 (rtdclk) p83 (rxd0) p86 (rxd1) p124 - p127 (tclk0-tclk3) p130 - p137 (tin16-tin23) p140 - p147 (tin8-tin15) p150 - p157 (tin0-tin7) p172, p173 (tin24, tin25) p175 (rxd2) p177 (rxd3) p190 - p197 (tin26-tin33) p201 (rxd4) p203 (rxd5) data bus (db0 - db15) operation mode register port output latch direction register input function enable peripheral function input data bus (db0 - db15) port output latch direction register input function enable
8 8-32 ver.0.10 input/output ports and pin functions 8.4 port peripheral circuits figure 8.4.2 port peripheral circuit diagram (2) note : denotes pins. ___ p64 (sbi) p221 / crx ____ p72 (hreq) sbi operation mode register hreq data bus (db0 - db15) port output latch direction register input function enable data bus (db0 - db15)
8 8-33 ver.0.10 input/output ports and pin functions 8.4 port peripheral circuits figure 8.4.3 port peripheral circuit diagram (3) note : denotes pins. ____ p71 (wait) __ p70 (bclk / wr) ____ p73 (hack) p74 (rtdtxd) p76 (rtdack) p82 (txd0) p85 (txd1) p93 - p97 (to16-to20) p100 - p107 (to8-to15) p110 - p117 (to0-to7) p160 - p167 (to21 - to28) p174 (txd2) p176 (txd3) p180 - p187 (to29-to36) p200 (txd4) p202 (txd5) p210 - p217 (to37-to44) p220 (ctx) wait data bus (db0 - db15) operation mode register port output latch direction register input function enable peripheral function input data bus (db0 - db15) port output latch direction register input function enable operation mode register
8 8-34 ver.0.10 input/output ports and pin functions 8.4 port peripheral circuits figure 8.4.4 port peripheral circuit diagram (4) note : denotes pins. p84 (sclki0, sclko0) p87 (sclki1, sclko1) p65 (sclki14, sclko4) p66 (sclki15, sclko5) mod0 mod1 fp _____ reset sclkii input sclkoi output reset mod0 , mod1 fp operation mode register data bus (db0 - db15) port output latch direction register input function enable uart/csio function select bit internal/external clock select bit
chapter 9 chapter 9 dmac 9.1 outline of the dmac 9.2 dmac related registers 9.3 functional description of the dmac 9.4 precautions about the dmac
9 9-2 ver.0.10 9.1 outline of the dmac the 32170 contains a 10 channel-dma (direct memory access) controller. it allows you to transfer data at high speed between internal peripheral i/os, between internal ram and internal peripheral i/o, and between internal rams, as requested by a software trigger or from an internal peripheral i/o. table 9.1.1 outline of the dmac item description number of channel 10 channels transfer request ? software trigger ? request from internal peripheral i/os: a-d converter, multijunction timer, or serial i/o (reception completed, transmit buffer empty) ? transfer operation can be cascaded between dma channels (note) maximum number 256 times of times transferred transferable ? 64 kbytes (address space from h'0080 0000 to h'0080 ffff) address space ? transfers between internal peripheral i/os, between internal ram and internal peripheral i/o, between internal rams are supported transfer data size 16 or 8 bits transfer method single transfer dma (control of the internal bus is relinquished for each transfer performed), dual-address transfer transfer mode single transfer mode direction of transfer one of three modes can be selected for the source and destination: ? address fixed ? address incremental ? ring buffered channel priority channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (priority is fixed) maximum transfer rate 13.3 mbytes per second (with 20 mhz internal peripheral clock) interrupt request group interrupt request can be generated when each transfer count register underflows. transfer area 64 kbytes from h'0080 0000 to h'0080 ffff (transferable in the entire internal ram/sfr area) note: transfer operation can be cascaded between dma channels as shown below. completion of one transfer in channel 0 starts dma transfer in channel 1 completion of one transfer in channel 1 starts dma transfer in channel 2 completion of one transfer in channel 2 starts dma transfer in channel 0 completion of one transfer in channel 3 starts dma transfer in channel 4 completion of one transfer in channel 5 starts dma transfer in channel 6 completion of one transfer in channel 6 starts dma transfer in channel 7 completion of one transfer in channel 7 starts dma transfer in channel 5 completion of one transfer in channel 8 starts dma transfer in channel 9 completion of all dma transfers in channel 0 (transfer count register underflow) starts dma transfer in channel 5 dmac 9.1 outline of the dmac
9 9-3 ver.0.10 dmac 9.1 outline of the dmac figure 9.1.1 block diagram of the dmac dma request selector a-d conversion completed dma channel 0 software start mjt (tin13 input signal) one dma0 transfer completed internal bus software start software start serial i/o0 (reception completed) one dma2 transfer completed one dma3 transfer completed mjt (tio8_udf) mjt (input event bus 2) mjt (output event bus 0) mjt (tin19 input signal) software start mjt (tin18 input signal) one dma1 transfer completed mjt (output event bus 1) software start serial i/o0 (transmit buffer empty) serial i/o1 (reception completed) source address register destination address register determination block dma start mjt (tin0 input signal) all dma0 transfers completed (udf) software start mjt (tin1 input signal) one dma5 transfer completed software start one dma7 transfer completed serial i/o2 (reception completed) mjt (tin20 input signal) serial i/o1 (transmit buffer empty) software start mjt (tin2 input signal) one dma6 transfer completed serial i/o2 (transmit buffer empty) software start mjt (input event bus 0) serial i/o3 (reception completed) mjt (tin7 input signal) source destination transfer count interrupt request internal bus arbitration software start mjt (tin8 input signal) one dma8 transfer completed serial i/o3 (transmit buffer empty) transfer count register udf dma request selector dma channel 1 udf source destination transfer count dma request selector dma channel 2 udf source destination transfer count dma request selector dma channel 3 udf source destination transfer count dma request selector dma channel 4 udf source destination transfer count dma request selector dma channel 5 udf source destination transfer count dma request selector dma channel 6 udf source destination transfer count dma request selector dma channel 7 udf source destination transfer count dma request selector dma channel 8 udf source destination transfer count dma request selector dma channel 9 udf determination block dma start internal bus arbitration interrupt request
9 9-4 ver.0.10 dmac 9.2 dmac related registers 9.2 dmac related registers the diagram below shows a memory map of dmac related registers. figure 9.2.1 dmac related register map (1/2) address d0 d7 +0 address +1 address d8 d15 note: the re g isters enclosed in thick frames can only be accessed in halfwords. dma0-4 interrupt request status register (dm04itst) h'0080 0400 h'0080 0414 h'0080 0416 h'0080 0418 h'0080 0410 h'0080 0412 h'0080 0422 h'0080 0424 h'0080 0426 h'0080 0428 h'0080 042a h'0080 0420 h'0080 0432 h'0080 0434 h'0080 0436 h'0080 0438 h'0080 043a h'0080 0430 h'0080 0408 h'0080 042c h'0080 042e h'0080 043c h'0080 043e h'0080 041a h'0080 041c h'0080 041e blank addresses are reserved. dma0 source address register (dm0sa) dma0 destination address register (dm0da) dma0-4 interrupt mask register (dm04itmk) dma5-9 interrupt request status register (dm59itst) dma5-9 interrupt mask register (dm59itmk) dma0 channel control register (dm0cnt) dma0 transfer count register (dm0tct) dma5 source address register (dm5sa) dma5 destination address register (dm5da) dma5 channel control register (dm5cnt) dma5 transfer count register (dm5tct) dma1 source address register (dm1sa) dma1 destination address register (dm1da) dma1 channel control register (dm1cnt) dma1 transfer count register (dm1tct) dma6 source address register (dm6sa) dma6 destination address register (dm6da) dma6 channel control register (dm6cnt) dma6 transfer count register (dm6tct) dma2 source address register (dm2sa) dma2 destination address register (dm2da) dma2 channel control register (dm2cnt) dma2 transfer count register (dm2tct) dma7 source address register (dm7sa) dma7 destination address register (dm7da) dma7 channel control register (dm7cnt) dma7 transfer count register (dm7tct)
9 9-5 ver.0.10 dmac 9.2 dmac related registers figure 9.2.2 dmac related register map (2/2) address d0 d7 +0 address +1 address d8 d15 note: the registers enclosed in thick frames can only be accessed in halfwords. h'0080 0440 h'0080 044c h'0080 044e h'0080 0450 h'0080 0448 h'0080 044a h'0080 045a h'0080 045c h'0080 045e h'0080 0460 h'0080 0462 h'0080 0458 h'0080 0470 h'0080 0472 h'0080 0474 h'0080 0476 h'0080 0468 h'0080 0444 h'0080 0464 h'0080 0466 h'0080 0478 h'0080 0452 h'0080 0454 h'0080 0456 blank addresses are reserved. dma3 source address register (dm3sa) dma3 destination address register (dm3da) dma3 channel control register (dm3cnt) dma3 transfer count register (dm3tct) dma8 source address register (dm8sa) dma8 destination address register (dm8da) dma8 channel control register (dm8cnt) dma8 transfer count register (dm8tct) dma4 source address register (dm4sa) dma4 destination address register (dm4da) dma4 channel control register (dm4cnt) dma4 transfer count register (dm4tct) dma9 source address register (dm9sa) dma9 destination address register (dm9da) dma9 channel control register (dm9cnt) dma9 transfer count register (dm9tct) dma0 software request generation register (dm0sri) h'0080 0442 h'0080 0446 dma1 software request generation register (dm1sri) dma2 software request generation register (dm2sri) dma3 software request generation register (dm3sri) dma4 software request generation register (dm4sri) dma5 software request generation register (dm5sri) dma6 software request generation register (dm6sri) dma7 software request generation register (dm7sri) dma8 software request generation register (dm8sri) dma9 software request generation register (dm9sri)
9 9-6 ver.0.10 dmac 9.2 dmac related registers 9.2.1 dma channel control register n dma0 channel control register (dm0cnt) d0123456d7 mdsel0 treqf0 reqsl0 tenl0 tszsl0 sadsl0 dadsl0 d bit name function r w 0 mdsel0 0 : normal mode (selects dma0 transfer mode) 1 : ring buffer mode 1 treqf0 0 : not requested (dma0 transfer request flag) 1 : requested 2, 3 reqsl0 00 : software start or one dma2 transfer completed (selects cause of dma0 request) 01 : a-d0 conversion completed 10 : mjt (tio8_udf) 11 : mjt (input event bus 2) 4 tenl0 0 : disables transfer (enables dma0 transfer) 1 : enables transfer 5 tszsl0 0 : 16 bits (selects dma0 transfer size) 1 : 8 bits 6 sadsl0 0 : fixed (selects dma0 source address direction) 1 : incremental 7 dadsl0 0 : fixed (selects dma0 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-7 ver.0.10 dmac 9.2 dmac related registers n dma1 channel control register (dm1cnt) d0123456d7 mdsel1 treqf1 reqsl1 tenl1 tszsl1 sadsl1 dadsl1 d bit name function r w 0 mdsel1 0 : normal mode (selects dma1 transfer mode) 1 : ring buffer mode 1 treqf1 0 : not requested (dma1 transfer request flag) 1 : requested 2, 3 reqsl1 00 : software start (selects cause of dma1 request) 01 : mjt (output event bus 0) 10 : mjt (tin13 input signal) 11 : one dma0 transfer completed 4 tenl1 0 : disables transfer (enables dma1 transfer) 1 : enables transfer 5 tszsl1 0 : 16 bits (selects dma1 transfer size) 1 : 8 bits 6 sadsl1 0 : fixed (selects dma1 source address direction) 1 : incremental 7 dadsl1 0 : fixed (selects dma1 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-8 ver.0.10 dmac 9.2 dmac related registers n dma2 channel control register (dm2cnt) d0123456d7 mdsel2 treqf2 reqsl2 tenl2 tszsl2 sadsl2 dadsl2 d bit name function r w 0 mdsel2 0 : normal mode (selects dma2 transfer mode) 1 : ring buffer mode 1 treqf2 0 : not requested (dma2 transfer request flag) 1 : requested 2, 3 reqsl2 00 : software start (selects cause of dma2 request) 01 : mjt (output event bus 1) 10 : mjt (tin18 input signal) 11 : one dma1 transfer completed 4 tenl2 0 : disables transfer (enables dma2 transfer) 1 : enables transfer 5 tszsl2 0 : 16 bits (selects dma2 transfer size) 1 : 8 bits 6 sadsl2 0 : fixed (selects dma2 source address direction) 1 : incremental 7 dadsl2 0 : fixed (selects dma2 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-9 ver.0.10 dmac 9.2 dmac related registers n dma3 channel control register (dm3cnt) d0123456d7 mdsel3 treqf3 reqsl3 tenl3 tszsl3 sadsl3 dadsl3 d bit name function r w 0 mdsel3 0 : normal mode (selects dma3 transfer mode) 1 : ring buffer mode 1 treqf3 0 : not requested (dma3 transfer request flag) 1 : requested 2, 3 reqsl3 00 : software start (selects cause of dma3 request) 01 : serial i/o0 (transmit buffer empty) 10 : serial i/o1 (reception completed) 11 : mjt (tin0 input signal) 4 tenl3 0 : disables transfer (enables dma3 transfer) 1 : enables transfer 5 tszsl3 0 : 16 bits (selects dma3 transfer size) 1 : 8 bits 6 sadsl3 0 : fixed (selects dma3 source address direction) 1 : incremental 7 dadsl3 0 : fixed (selects dma3 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-10 ver.0.10 dmac 9.2 dmac related registers n dma4 channel control register (dm4cnt) d0123456d7 mdsel4 treqf4 reqsl4 tenl4 tszsl4 sadsl4 dadsl4 d bit name function r w 0 mdsel4 0 : normal mode (selects dma4 transfer mode) 1 : ring buffer mode 1 treqf4 0 : not requested (dma4 transfer request flag) 1 : requested 2, 3 reqsl4 00 : software start (selects cause of dma4 request) 01 : one dma3 transfer completed 10 : serial i/o0 (reception completed) 11 : mjt (tin19 input signal) 4 tenl4 0 : disables transfer (enables dma4 transfer) 1 : enables transfer 5 tszsl4 0 : 16 bits (selects dma4 transfer size) 1 : 8 bits 6 sadsl4 0 : fixed (selects dma4 source address direction) 1 : incremental 7 dadsl4 0 : fixed (selects dma4 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-11 ver.0.10 dmac 9.2 dmac related registers n dma5 channel control register (dm5cnt) d0123456d7 mdsel5 treqf5 reqsl5 tenl5 tszsl5 sadsl5 dadsl5 d bit name function r w 0 mdsel5 0 : normal mode (selects dma5 transfer mode) 1 : ring buffer mode 1 treqf5 0 : not requested (dma5 transfer request flag) 1 : requested 2, 3 reqsl5 00 : software start or one dma7 transfer completed (selects cause of dma5 request) 01 : all dma0 transfers completed 10 : serial i/o2 (reception completed) 11 : mjt (tin20 input signal) 4 tenl5 0 : disables transfer (enables dma5 transfer) 1 : enables transfer 5 tszsl5 0 : 16 bits (selects dma5 transfer size) 1 : 8 bits 6 sadsl5 0 : fixed (selects dma5 source address direction) 1 : incremental 7 dadsl5 0 : fixed (selects dma5 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-12 ver.0.10 dmac 9.2 dmac related registers n dma6 channel control register (dm6cnt) d0123456d7 mdsel6 treqf6 reqsl6 tenl6 tszsl6 sadsl6 dadsl6 d bit name function r w 0 mdsel6 0 : normal mode (selects dma6 transfer mode) 1 : ring buffer mode 1 treqf6 0 : not requested (dma6 transfer request flag) 1 : requested 2, 3 reqsl6 00 : software start (selects cause of dma6 request) 01 : serial i/o1 (transmit buffer empty) 10 : mjt (tin1 input signal) 11 : one dma5 transfer completed 4 tenl6 0 : disables transfer (enables dma6 transfer) 1 : enables transfer 5 tszsl6 0 : 16 bits (selects dma6 transfer size) 1 : 8 bits 6 sadsl6 0 : fixed (selects dma6 source address direction) 1 : incremental 7 dadsl6 0 : fixed (selects dma6 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-13 ver.0.10 dmac 9.2 dmac related registers n dma7 channel control register (dm7cnt) d0123456d7 mdsel7 treqf7 reqsl7 tenl7 tszsl7 sadsl7 dadsl7 d bit name function r w 0 mdsel7 0 : normal mode (selects dma7 transfer mode) 1 : ring buffer mode 1 treqf7 0 : not requested (dma7 transfer request flag) 1 : requested 2, 3 reqsl7 00 : software start (selects cause of dma7 request) 01 : serial i/o2 (transmit buffer empty) 10 : mjt (tin2 input signal) 11 : one dma6 transfer completed 4 tenl7 0 : disables transfer (enables dma7 transfer) 1 : enables transfer 5 tszsl7 0 : 16 bits (selects dma7 transfer size) 1 : 8 bits 6 sadsl7 0 : fixed (selects dma7 source address direction) 1 : incremental 7 dadsl7 0 : fixed (selects dma7 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-14 ver.0.10 dmac 9.2 dmac related registers n dma8 channel control register (dm8cnt) d0123456d7 mdsel8 treqf8 reqsl8 tenl8 tszsl8 sadsl8 dadsl8 d bit name function r w 0 mdsel8 0 : normal mode (selects dma8 transfer mode) 1 : ring buffer mode 1 treqf8 0 : not requested (dma8 transfer request flag) 1 : requested 2, 3 reqsl8 00 : software start (selects cause of dma8 request) 01 : mjt (input event bus 0) 10 : serial i/o3 (reception completed) 11 : mjt (tin7 input signal) 4 tenl8 0 : disables transfer (enables dma8 transfer) 1 : enables transfer 5 tszsl8 0 : 16 bits (selects dma8 transfer size) 1 : 8 bits 6 sadsl8 0 : fixed (selects dma8 source address direction) 1 : incremental 7 dadsl8 0 : fixed (selects dma8 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-15 ver.0.10 dmac 9.2 dmac related registers n dma9 channel control register (dm9cnt) d0123456d7 mdsel9 treqf9 reqsl9 tenl9 tszsl9 sadsl9 dadsl9 d bit name function r w 0 mdsel9 0 : normal mode (selects dma9 transfer mode) 1 : ring buffer mode 1 treqf9 0 : not requested (dma9 transfer request flag) 1 : requested 2, 3 reqsl9 00 : software start (selects cause of dma9 request) 01 : serial i/o3 (transmit buffer empty) 10 : mjt (tin8 input signal) 11 : one dma8 transfer completed 4 tenl9 0 : disables transfer (enables dma9 transfer) 1 : enables transfer 5 tszsl9 0 : 16 bits (selects dma7 transfer size) 1 : 8 bits 6 sadsl9 0 : fixed (selects dma7 source address direction) 1 : incremental 7 dadsl9 0 : fixed (selects dma9 destination 1 : incremental address direction) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
9 9-16 ver.0.10 dmac 9.2 dmac related registers the dma channel control register consists of bits to select dma transfer mode in each channel, set dma transfer request flag, and the bits to select the cause of dma request, enable dma transfer, and set the transfer size and the source/destination address directions. (1) mdseln (dman transfer mode select) bit (d0) this bit when in single transfer mode selects normal mode or ring buffer mode. normal mode is selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1. in ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. in this case, the transfer count register counts in free-run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). no interrupt is generated at completion of dma transfer. (2) treqfn (dman transfer request flag) bit (d1) this flag is set to 1 when a dma transfer request occurs. reading this flag helps to know dma transfer requests in each channel. the generated dma request is cleared by writing a 0 to this bit. if you write a 1, the value you wrote is ignored and the bit retains its previous value. if a new dma transfer request is generated for a channel whose dma transfer request flag has already been set to 1, the next dma transfer request is not accepted until the transfer under way in that channel is completed. (3) reqsln (cause of dman request select) bits (d2, d3) these bits select the cause of dma request in each dma channel. (4) tenln (dman transfer enable) bit (d4) transfer is enabled by setting this bit to 1, so that the channel is ready for dma transfer. conversely, transfer is disabled by setting this bit to 0. however, if a transfer request has already been accepted, transfer in that channel is not disabled until after the requested transfer is completed. (5) tszsln (dman transfer size select) bit (d5) this bit selects the number of bits to be transferred in one dma transfer operation (unit of one transfer). the unit of one transfer is 16 bits when tszsl = 0 or 8 bits when tszsl = 1. (6) sadsln (dman source address direction select) bit (d6) this bit selects the direction in which the source address changes as transfer proceeds. this mode can be selected from two choices: address fixed or address incremental. (7) dadsln (damn destination address direction select) bit (d7) this bit selects the direction in which the destination address changes as transfer proceeds. this mode can be selected from two choices: address fixed or address incremental.
9 9-17 ver.0.10 dmac 9.2 dmac related registers 9.2.2 dma software request generation registers n dma0 software request generation register (dm0sri) n dma1 software request generation register (dm1sri) n dma2 software request generation register (dm2sri) n dma3 software request generation register (dm3sri) n dma4 software request generation register (dm4sri) n dma5 software request generation register (dm5sri) n dma6 software request generation register (dm6sri) n dma7 software request generation register (dm7sri) n dma8 software request generation register (dm8sri) n dma9 software request generation register (dm9sri) d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 dm0sri - dm9sri d bit name function r w 0 - 15 dm0sri - dm9sri dma transfer request is generated ? (generates dma software request) by writing any data note: this register can be accessed in either bytes or halfwords. the dma software request generation register is used to generate dma transfer requests in software. a dma transfer request can be generated by writing any data to this register when "software start" has been selected for the cause of dma request. dm0sri - dm9sri (dma software request generate) bit a software dma transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "software" is selected as the cause of dma transfer request (by setting the dma channel control register d2, d3 bits to "00").
9 9-18 ver.0.10 dmac 9.2 dmac related registers 9.2.3 dma source address registers n dma0 source address register (dm0sa) n dma1 source address register (dm1sa) n dma2 source address register (dm2sa) n dma3 source address register (dm3sa) n dma4 source address register (dm4sa) n dma5 source address register (dm5sa) n dma6 source address register (dm6sa) n dma7 source address register (dm7sa) n dma8 source address register (dm8sa) n dma9 source address register (dm9sa) d01234567891011121314d15 dm0sa - dm9sa d bit name function r w 0 - 15 dm0sa - dm9sa a16-a31 of the source address (a0-a15 are fixed to h'0080) note: this register must always be accessed in halfwords. the dma source address register is used to set the source address of dma transfer in such a way that d0 corresponds to a16, and d15 corresponds to a31. because this register is comprised of a current register, the value you get by reading this register is always the current value. when dma transfer finishes (at which the transfer count register underflows), the value in this register if "address fixed" is selected, is the same source address that was set in it before dma transfer began; if "address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). make sure the dma source address register is always accessed in halfwords (16 bits) beginning with an even address. if accessed in bytes, the value read from this register is indeterminate. dm0sa-dm9sa (a16-a31 of the source address) by setting this register, specify the source address of dma transfer in internal i/o space ranging from h'0080 0000 to h'0080 ffff or in the ram space. the 16 high-order bits of the source address (a0-a15) are always fixed to h'0080. use this register to set the 16 low-order bits of the source address (with d0 corresponding to a16, and d15 corresponding to a31).
9 9-19 ver.0.10 dmac 9.2 dmac related registers 9.2.4 dma destination address registers n dma0 destination address register (dm0da) n dma1 destination address register (dm1da) n dma2 destination address register (dm2da) n dma3 destination address register (dm3da) n dma4 destination address register (dm4da) n dma5 destination address register (dm5da) n dma6 destination address register (dm6da) n dma7 destination address register (dm7da) n dma8 destination address register (dm8da) n dma9 destination address register (dm9da) d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 dm0da - dm9da d bit name function r w 0 - 15 dm0da - dm9da a16-a31 of the destination address (a0-a15 are fixed to h'0080) note: this register must always be accessed in halfwords. the dma destination address register is used to set the destination address of dma transfer in such a way that d0 corresponds to a16, and d15 corresponds to a31. because access to this register is comprised of a current register, the value you get by reading this register is always the current value. when dma transfer finishes (at which the transfer count register underflows), the value in this register if "address fixed" is selected, is the same destination address that was set in it before dma transfer began; if "address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). make sure the dma destination address register is always accessed in halfwords (16 bits) beginning with an even address. if accessed in bytes, the value read from this register is indeterminate. dm0da-dm9da (a16-a31 of the destination address) by setting this register, specify the destination address of dma transfer in internal i/o space ranging from h'0080 0000 to h'0080 ffff or in the ram space. the 16 high-order bits of the destination address (a0-a15) are always fixed to h'0080. use this register to set the 16 low-order bits of the destination address (with d0 corresponding to a16, and d15 corresponding to a31).
9 9-20 ver.0.10 dmac 9.2 dmac related registers 9.2.5 dma transfer count registers n dma0 transfer count register (dm0tct) n dma1 transfer count register (dm1tct) n dma2 transfer count register (dm2tct) n dma3 transfer count register (dm3tct) n dma4 transfer count register (dm4tct) n dma5 transfer count register (dm5tct) n dma6 transfer count register (dm6tct) n dma7 transfer count register (dm7tct) n dma8 transfer count register (dm8tct) n dma9 transfer count register (dm9tct) d8 9 1011121314d15 dm0tct - dm9tct d bit name function r w 8 - 15 dm0tct - dm9tct dma transfer count (ignored during 32-channel ring buffer mode) the dma transfer count register is used to set the number of times data is transferred in each channel. however, the value in this register is ignored during ring buffer mode. the transfer count is the (value set in the transfer count register + 1). because the dma transfer count register is comprised of a current register, the value you get by reading this register is always the current value. (however, if you read this register in a cycle immediately after transfer, the value you get is the value that was in the count register before the transfer began.) when transfer finishes, this count register underflows, so that the read value you get is h'ff. if any cascaded channel exists, each time one dma transfer (byte or halfword) is completed or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts.
9 9-21 ver.0.10 9.2.6 dma interrupt request status registers n dma0-4 interrupt request status register (dm04itst) d0123456d7 dmitst4 dmitst3 dmitst2 dmitst1 dmitst0 d bit name function r w 0 - 2 no functions assigned 0 3 dmitst4 (dma4 interrupt request status) 0 : no interrupt request 4 dmitst3 (dma3 interrupt request status) 1 : interrupt requested 5 dmitst2 (dma2 interrupt request status) 6 dmitst1 (dma1 interrupt request status) 7 dmitst0 (dma0 interrupt request status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. the dma0-4 interrupt request status register lets you know the status of interrupt requests in channels 0-4. if the dman interrupt request status bit (n = 0 to 4) is set to 1, it means that a dman interrupt request in the corresponding channel has been generated. dmitstn (dman interrupt request status) bit (n = 0 to 4) [setting the dman interrupt request status bit] this bit can only be set in hardware, and cannot be set in software. [clearing the dman interrupt request status bit] this bit is cleared by writing a 0 in software. note: the dman interrupt request status bit cannot be cleared by writing a 0 to the "interrupt cause bit" of the dma interrupt control register that the interrupt controller has. when writing to the dma0-4 interrupt request status register, be sure to set the bits you want to clear to 0 and all other bits to 1. the bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. dmac 9.2 dmac related registers
9 9-22 ver.0.10 dmac 9.2 dmac related registers n dma5-9 interrupt request status register (dm59itst) d0123456d7 dmitst9 dmitst8 dmitst7 dmitst6 dmitst5 d bit name function r w 0 - 2 no functions assigned 0 3 dmitst9 (dma9 interrupt request status) 0 : no interrupt request 4 dmitst8 (dma8 interrupt request status) 1 : interrupt requested 5 dmitst7 (dma7 interrupt request status) 6 dmitst6 (dma6 interrupt request status) 7 dmitst5 (dma5 interrupt request status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. the dma5-9 interrupt request status register lets you know the status of interrupt requests in channels 5-9. if the dman interrupt request status bit (n = 5 to 9) is set to 1, it means that a dman interrupt request in the corresponding channel has been generated. dmitstn (dman interrupt request status) bit (n = 5 to 9) [setting the dman interrupt request status bit] this bit can only be set in hardware, and cannot be set in software. [clearing the dman interrupt request status bit] this bit is cleared by writing a 0 in software. note: the dman interrupt request status bit cannot be cleared by writing a 0 to the "interrupt cause bit" of the dma interrupt control register that the interrupt controller has. when writing to the dma5-9 interrupt request status register, be sure to set the bits you want to clear to 0 and all other bits to 1. the bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote.
9 9-23 ver.0.10 dmac 9.2 dmac related registers 9.2.7 dma interrupt mask registers n dma0-4 interrupt mask register (dm04itmk) d8 9 1011121314d15 dmitmk4 dmitmk3 dmitmk2 dmitmk1 dmitmk0 d bit name function r w 8 - 10 no functions assigned 0 11 dmitmk4 (dma4 interrupt request mask) 0 : enables interrupt request 12 dmitmk3 (dma3 interrupt request mask) 1 : masks (disables) interrupt request 13 dmitmk2 (dma2 interrupt request mask) 14 dmitmk1 (dma1 interrupt request mask) 15 dmitmk0 (dma0 interrupt request mask) the dma0-4 interrupt mask register is used to mask interrupt requests in dma channels 0-4. dmitmkn (dman interrupt request mask) bit (n = 0 to 4) dman interrupt request is masked by setting the dman interrupt request mask bit to 1. however, when an interrupt request is generated, the dman interrupt request status bit is always set to 1 irrespective of the contents of this register.
9 9-24 ver.0.10 dmac 9.2 dmac related registers n dma5-9 interrupt mask register (dm59itmk) d8 9 1011121314d15 dmitmk9 dmitmk8 dmitmk7 dmitmk6 dmitmk5 d bit name function r w 8 - 10 no functions assigned 0 11 dmitmk9 (dma9 interrupt request mask) 0 : enables interrupt request 12 dmitmk8 (dma8 interrupt request mask) 1 : masks (disables) interrupt request 13 dmitmk7 (dma7 interrupt request mask) 14 dmitmk6 (dma6 interrupt request mask) 15 dmitmk5 (dma5 interrupt request mask) the dma5-9 interrupt mask register is used to mask interrupt requests in dma channels 5-9. dmitmkn (dman interrupt request mask) bit (n = 5 to 9) dman interrupt request is masked by setting the dman interrupt request mask bit to 1. however, when an interrupt request is generated, the dman interrupt request status bit is always set to 1 irrespective of the contents of this register.
9 9-25 ver.0.10 dmac 9.2 dmac related registers figure 9.2.3 block diagram of dma transfer interrupt 0 b3 dmitst4 f/f dmitmk4 f/f b11 b4 dmitst3 f/f dmitmk3 f/f b12 b5 dmitst2 f/f dmitmk2 f/f b13 b6 dmitst1 f/f dmitmk1 f/f b14 b7 dmitst0 f/f dmitmk0 f/f b15 dm04itst dm04itmk dma4udf dma3udf dma2udf dma1udf dma0udf data bus dma transfer interrupt 0 (level) 5-source inputs
9 9-26 ver.0.10 dmac 9.2 dmac related registers figure 9.2.4 block diagram of dma transfer interrupt 1 b3 dmitst9 f/f dmitmk9 f/f b11 b4 dmitst8 f/f dmitmk8 f/f b12 b5 dmitst7 f/f dmitmk7 f/f b13 b6 dmitst6 f/f dmitmk6 f/f b14 b7 dmitst5 f/f dmitmk5 f/f b15 dm59itst dm59itmk dma9udf dma8udf dma7udf dma6udf dma5udf data bus dma transfer interrupt 1 (level) 5-source inputs
9 9-27 ver.0.10 dmac 9.3 functional description of the dmac 9.3 functional description of the dmac 9.3.1 cause of dma request for each dma channel (channels 0 to 9), dma transfer can be requested from multiple sources. there are various causes (or sources) of dma transfer, so that dma transfer can be started by a request from internal peripheral i/o, started in software by a program, or can be started upon completion of one transfer or all transfers in a dma channel (cascade mode). the cause of dma request is selected using the cause of request select bit provided for each channel, reqsln (dman channel control register bits d2, d3). the table below lists the causes of dma requests in each channel. table 9.3.1 causes of dma requests in dma0 and generation timings reqsl0 cause of dma request dma request generation timing 0 0 software start when any data is written to dma0 software request or one dma2 transfer completed generation register (software start) or one dma2 transfer is completed (cascade mode) 0 1 a-d0 conversion completed when a-d0 conversion is completed 1 0 mjt (tio8_udf) when mjt tio8 underflow occurs 1 1 mjt (input event bus 2) when mjt's input event bus 2 signal is generated table 9.3.2 causes of dma requests in dma1 and generation timings reqsl1 cause of dma request dma request generation timing 0 0 software start when any data is written to dma1 software request generation register 0 1 mjt (output event bus 0) when mjt's output event bus 0 signal is generated 1 0 mjt (tin13 input signal) when mjt's tin13 input signal is generated 1 1 one dma0 transfer completed when one dma0 transfer is completed (cascade mode)
9 9-28 ver.0.10 dmac 9.3 functional description of the dmac table 9.3.3 causes of dma requests in dma2 and generation timings reqsl2 cause of dma request dma request generation timing 0 0 software start when any data is written to dma2 software request generation register 0 1 mjt (output event bus 1) when mjt's output event bus 1 signal is generated 1 0 mjt (tin18 input signal) when mjt's tin18 input signal is generated 1 1 one dma1 transfer completed when one dma1 transfer is completed (cascade mode) table 9.3.4 causes of dma requests in dma3 and generation timings reqsl3 cause of dma request dma request generation timing 0 0 software start when any data is written to dma3 software request generation register 0 1 serial i/o0 (transmit buffer empty) when serial i/o0 transmit buffer is emptied 1 0 serial i/o1 (reception completed) when serial i/o1 reception is completed 1 1 mjt (tin0 input signal) when mjt's tin0 input signal is generated table 9.3.5 causes of dma requests in dma4 and generation timings reqsl4 cause of dma request dma request generation timing 0 0 software start when any data is written to dma4 software request generation register 0 1 one dma3 transfer completed when one dma3 transfer is completed (cascade mode) 1 0 serial i/o0 (reception completed) when serial i/o0 reception is completed 1 1 mjt (tin19 input signal) when mjt's tin19 input signal is generated
9 9-29 ver.0.10 dmac 9.3 functional description of the dmac table 9.3.6 causes of dma requests in dma5 and generation timings reqsl5 cause of dma request dma request generation timing 0 0 software start when any data is written to dma5 software request or one dma7 transfer completed generation register or one dma7 transfer is completed (cascade mode) 0 1 all dma0 transfers completed when all dma0 transfers are completed (cascade mode) 1 0 serial i/o2 (reception completed) when serial i/o2 reception is completed 1 1 mjt (tin20 input signal) when mjt's tin20 input signal is generated table 9.3.7 causes of dma requests in dma6 and generation timings reqsl6 cause of dma request dma request generation timing 0 0 software start when any data is written to dma6 software request generation register 0 1 serial i/o1 (transmit buffer empty) when serial i/o1 transmit buffer is emptied 1 0 mjt (tin1 input signal) when mjt's tin1 input signal is generated 1 1 one dma5 transfer completed when one dma5 transfer is completed (cascade mode) table 9.3.8 causes of dma requests in dma7 and generation timings reqsl7 cause of dma request dma request generation timing 0 0 software start when any data is written to dma7 software request generation register 0 1 serial i/o2 (transmit buffer empty) when serial i/o2 transmit buffer is emptied 1 0 mjt (tin2 input signal) when mjt's tin2 input signal is generated 1 1 one dma6 transfer completed when one dma6 transfer is completed (cascade mode)
9 9-30 ver.0.10 dmac 9.3 functional description of the dmac table 9.3.9 causes of dma requests in dma8 and generation timings reqsl8 cause of dma request dma request generation timing 0 0 software start when any data is written to dma8 software request generation register 0 1 mjt (input event bus 0) when mjt's input event bus 0 signal is generated 1 0 serial i/o3 (reception completed) when serial i/o3 reception is completed 1 1 mjt (tin7 input signal) when mjt's tin7 input signal is generated table 9.3.10 causes of dma requests in dma9 and generation timings reqsl9 cause of dma request dma request generation timing 0 0 software start when any data is written to dma9 software request generation register 0 1 serial i/o3 (transmit buffer empty) when serial i/o3 transmit buffer is emptied 1 0 mjt (tin8 input signal) when mjt's tin8 input signal is generated 1 1 one dma8 transfer completed when one dma8 transfer is completed (cascade mode)
9 9-31 ver.0.10 dmac 9.3 functional description of the dmac 9.3.2 dma transfer processing procedure shown below is an example of how to control dma transfer in cases when performing transfer in dma channel 0. figure 9.3.1 example of a dma transfer processing procedure dma transfer starts as requested by internal peripheral i/o dma transfer processing starts transfer count register underflows interrupt request generated set dma0 channel control register set dma0-4 interrupt request status register set dma0 channel control register set dma0 source address register set dma0 destination address register set dma0 count register setting dmac related registers starting dma transfer dma transfer completed ?transfers disabled ?clears interrupt request status bit set dma0-4 interrupt mask register ?source address of transfer ?address ?number of times dma transfer performed ?transfer mode, cause of request, transfer size, address direction, and transfer enable dma operation completed ?enables interrupt request set the interrupt controller's dma0-4 interrupt control register ?interrupt priority level setting interrupt controller related registers
9 9-32 ver.0.10 dmac 9.3 functional description of the dmac figure 9.3.2 gaining and releasing control of the internal bus 9.3.3 starting dma use the reqsl (cause of dma request select) bit to set the cause of dma request. to enable dma, set the tenl (dma transfer enable) bit to 1. dma transfer begins when the specified cause of dma request becomes effective after setting the tenl (dma transfer enable) bit to 1. 9.3.4 channel priority channel 0 has the highest priority. the priority of this and other channels is shown below. channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 this order of priority is fixed and cannot be changed. among channels for which dma transfers are requested, the channel that has the highest priority is selected. channel selection is made every transfer cycle (one dma bus cycle consisting of three machine cycles). 9.3.5 gaining and releasing control of the internal bus for any channel, control of the internal bus is gained and released in "single transfer dma" mode. in single transfer dma, the dma gains control of the internal bus when dma transfer request is accepted and after executing one dma transfer (consisting of one read cycle + one write cycle of internal peripheral clock), returns bus control to the cpu. the diagram below shows dma operation in single transfer dma. one dma transfer dmac cpu internal bus arbitration (control requested by dmac) internal bus r: read w: write rw rw rw requested gained released requested gained requested gained released released one dma transfer one dma transfer
9 9-33 ver.0.10 dmac 9.3 functional description of the dmac 9.3.6 transfer units use the tszsl (dma transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one dma transfer. 9.3.7 transfer counts use the dma transfer count register to set transfer counts for each channel. transfer can be performed up to 256 times. the value of the dma transfer count register is decremented by one each time one transfer unit is transferred. in ring buffer mode, the dma transfer count register operates in free-run mode, with the value set in it ignored. 9.3.8 address space the address space in which data can be transferred by dma is the internal peripheral i/o or 64 kbytes of ram space (h'0080 0000 through h'0080 ffff) for either source or destination. to set the source and destination addresses in each channel, use the dma source address register and dma destination address register. 9.3.9 transfer operation (1) dual-address transfer irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (the transfer data is temporarily taken into the dma's internal temporary register.) (2) bus protocol and bus timing because the bus interface is shared with the cpu, the same applies to both bus protocol and bus timing as in peripheral module access from the cpu. (3) transfer rate the maximum transfer rate is calculated using the equation below: 1 maximum transfer rate [bytes/second] = 2 bytes 1 / f (bclk) 3 cycles
9 9-34 ver.0.10 dmac 9.3 functional description of the dmac (4) address count direction and address changes the direction in which the source and destination addresses are counted as transfer proceeds ("address fixed" or "address incremental") is set for each channel using the sadsl (source address direction select) and dadsl (destination address select) bits. when the transfer size is 16 bits, the address is incremented by two for each dma transfer performed; when the transfer size is 8 bits, the address is incremented by one. table 9.3.11 address count direction and address changes address count direction transfer unit address change for one dma address fixed 8 bits 0 16 bits 0 address incremental 8 bits +1 16 bits +2 (5) transfer count value the transfer count value is decremented by one at a time irrespective of the size of transfer unit (8 or 16 bits).
9 9-35 ver.0.10 dmac 9.3 functional description of the dmac (6) transfer byte positions when the transfer unit = 8 bits, the lsb of the address register is effective for both source and destination. (therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) when the transfer unit = 8 bits, the lsb of the address register (d15 of the address register) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. the diagram below shows the valid transfer byte positions. figure 9.3.3 transfer byte positions d0 d7 d8 d15 8 bits + 0 + 1 source destination 16 bits d0 d7 d8 d15 + 0 + 1 8 bits 8 bits 8 bits 16 bits
9 9-36 ver.0.10 dmac 9.3 functional description of the dmac figure 9.3.4 example of address increment operation in 32-channel ring buffer mode (7) ring buffer mode when ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. in this case, however, the five low-order bits of the ring buffer start address must always be b'00000. the address increment operation in ring buffer mode is described below. when the transfer unit = 8 bits the 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. when as transfer proceeds the five low-order bits reach b'11111, they are recycled to b'00000 by the next increment operation, thus returning to the start address again. when the transfer unit = 16 bits the 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. when as transfer proceeds the six low-order bits reach b'111110, they are recycled to b'000000 by the next increment operation, thus returning to the start address again. when the source address has been set to be incremented, it is the source address that recycles to the start address; when the destination address has been set to be incremented, it is the destination address that recycles to the start address. if both source and destination addresses have been set to be incremented, both addresses recycle to the start address. however, the start address on either side must have their five low-order bits initially being b'00000. during ring buffer mode, the transfer count register is ignored. also, once dma operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to (to disable transfer). transfer count transfer address 1 h'0080 1000 2 h'0080 1001 3 h'0080 1002 || 31 h'0080 101e 32 h'0080 101f 1 h'0080 1000 2 h'0080 1001 || transfer count transfer address 1 h'0080 1000 2 h'0080 1002 3 h'0080 1004 || 31 h'0080 103c 32 h'0080 103e 1 h'0080 1000 2 h'0080 1002 ||
9 9-37 ver.0.10 dmac 9.3 functional description of the dmac 9.3.10 end of dma and interrupt in normal mode, dma transfer is terminated when the transfer count register underflows. when transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. also, an interrupt request is generated at completion of transfer. however, this interrupt is not generated for channels where interrupt requests have been masked by the dma interrupt mask register. during ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to 0 (to disable transfer). in this case, therefore, the dma transfer-completed interrupt request is not generated. nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 status of each register after completion of dma transfer when dma transfer is completed, the status of the source address and destination address registers becomes as follows: (1) address fixed ? the value set in the address register before dma transfer started remains intact (fixed). (2) address incremental ? for 8-bit transfer, the value of the address register is the last transfer address + 1. ? for 16-bit transfer, the value of the address register is the last transfer address + 2. the transfer count register when dma transfer completed is in an underflow state (h'ff). therefore, to perform another dma transfer, set the transfer count register newly again, except when you are performing transfers 256 times (h'ff).
9 9-38 ver.0.10 dmac 9.4 precautions about the dmac 9.4 precautions about the dmac ? about writing to dmac related registers because dma transfer involves exchanging data via the internal bus, basically you only can write to the dmac related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). when transfer is enabled, do not write to the dmac related registers because write operation to those registers, except the dma transfer enable bit, transfer request flag, and the dma transfer count register which is protected in hardware, is instable. the table below shows the registers that can or cannot be accessed for write. table 9.4.1 dmac related registers that can or cannot be accessed for write status transfer enable bit transfer request flag other dmac related registers when transfer is enabled 5 when transfer is disabled : can be accessed ; 5 : cannot be accessed for even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. dma channel control register's transfer enable bit and transfer request flag for all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. note that you only can write a 0 to the transfer request flag as valid data. dma transfer count register when transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. a rewriting the dma source and dma destination addresses on different channels by dma transfer in this case, you are writing to the dmac related registers while dma is enabled, but this practically does not present any problem. however, you cannot dma-transfer to the dmac related registers on the local channel itself in which you are currently operating.
9 9-39 ver.0.10 dmac 9.4 precautions about the dmac 9.4 precautions about the dmac ? manipulating dmac related registers by dma transfer when manipulating dmac related registers by means of dma transfer (e.g., reloading the dmac related registers' initial values by dma transfer), do not write to the dmac related registers on the local channel itself through that channel. (if this precaution is neglected, device operation cannot be guaranteed.) only if residing on other channels, you can write to the dmac related registers by means of dma transfer. (for example, you can rewrite the dman source address and dman destination address registers on channel 1 by dma transfer through channel 0.) ? about the dma interrupt request status register when clearing the dma interrupt request status register, be sure to write 1s to all bits but the one you want to clear. the bits to which you wrote 1s retain the previous data they had before the write. ? about the stable operation of dma transfer to ensure the stable operation of dma transfer, never rewrite the dmac related registers, except the dma channel control register's transfer enable bit, unless transfer is disabled. one exception is that even when transfer is enabled, you can rewrite the dma source address and dma destination address registers by dma transfer from one channel to another.
9 9-40 ver.0.10 dmac 9.4 precautions about the dmac * this is a blank page.*
chapter 10 chapter 10 multijunction timers 10.1 outline of multijunction timers 10.2 common units of multijunction timer 10.3 top (output-related 16-bit timer) 10.4 tio (input/output-related 16-bit timer) 10.5 tms (input-related 16-bit timer) 10.6 tml (input-related 32-bit timer) 10.7 tid (input-related 16-bit timer) 10.8 tod (output-related 16-bit timer) 10.9 tom (output-related 16-bit timer)
10 10-2 ver.0.10 10.1 outline of multijunction timers the multijunction timers (abbreviated mjt) have input event and output event buses. therefore, in addition to being used as a single unit, the timers can be internally connected to each other. this capability allows for highly flexible timer configuration, making it possible to meet various application needs. it is because the timers are connected to the internal event bus at multiple points that they are called the "multijunction" timers. the 32170 has seven types of multijunction timers as listed in the table below, providing a total of 64 channels of timers. table 10.1.1 outline of multijunction timers (1/2) name type number of channels description top output-related 11 one of three output modes can be selected by software. (timer output) 16-bit timer (down-counter) ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tio input/output-related 10 one of three input modes or four output modes can be (timer 16-bit timer selected by software. input output) (down-counter) ? measure clear input mode ? measure free-run input mode ? noise processing input mode ? pwm output mode ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tms input-related 8 16-bit input measure timer (timer 16-bit timer measure small) (up-counter) tml input-related 8 32-bit input measure timer (timer 32-bit timer measure large) (up-counter) multijunction timers 10.1 outline of multijunction timers
10 10-3 ver.0.10 multijunction timers 10.1 outline of multijunction timers table 10.1.1 outline of multijunction timers (2/2) name type number of channels description tid input-related 3 one of three input modes can be selected by software. (timer input 16-bit timer ? fixed period mode derivation) (up/down-counter) ? event count mode ? multiply-by-4 event count mode tod output-related 16 one of four output modes can be selected by software. (timer output 16-bit timer derivation) (down-counter) ? pwm output mode ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tom output-related 8 one of four output modes can be selected by software. (timer output 16-bit timer modification) (down-counter) ? pwm output mode ? single-shot pwm output mode ? single-shot output mode ? continuous output mode table 10.1.2 mjt interrupt generation functions of the m32170 signal name source of mjt interrupt requested interrupt controller (icu) input icu cause input irq18 tin30 - tin33 input tml1 input interrupt 4 irq17 tid2 output tid2 output interrupt 1 irq16 tod1_0 - tod1_7 output tod1+tom0 output interrupt 16 tom0_0 - tom0_7 output irq15 tid1 output tid1 output interrupt 1 irq14 tid0 output tid0 output interrupt 1 irq13 tod0_0 - tod0_7 output tod0 output interrupt 8 irq12 tin3 - tin6 input mjt input interrupt 4 4 irq11 tin20 - tin23 input mjt input interrupt 3 4 irq10 tin12 - tin19 input mjt input interrupt 2 8 irq9 tin0 - tin2 input mjt input interrupt 1 3 irq8 tin7 - tin11 input mjt input interrupt 0 5 irq7 tms0, tms1 output mjt output interrupt 7 2 irq6 top8, top9 output mjt output interrupt 6 2 irq5 top10 output mjt output interrupt 5 1 irq4 tio4 - 7 output mjt output interrupt 4 4 irq3 tio8, tio9 output mjt output interrupt 3 2 irq2 top0 - 5 output mjt output interrupt 2 6 irq1 top6, top7 output mjt output interrupt 1 2 irq0 tio0 - 3 output mjt output interrupt 0 4
10 10-4 ver.0.10 table 10.1.3 dma transfer request generation by mjt signal name source of dma request generated dmac input channel drq0 tio8 underflow channel 0 drq1 input event bus 2 channel 0 drq2 output event bus 0 channel 1 drq3 tin13 input channel 1 drq4 output event bus 1 channel 2 drq5 tin18 input channel 2 drq6 tin19 input channel 4 drq7 tin0 input channel 3 drq8 tin1 input channel 6 drq9 tin2 input channel 7 drq10 tin7 input channel 8 drq11 tin8 input channel 9 drq12 tin20 input channel 5 drq13 input event bus 0 channel 8 table 10.1.4 a-d conversion start request by mjt signal name source of a-d conversion start requested a-d converter ad0trg output event bus 3 can be input to a-d0 conversion start trigger ad1trg tid1 overflow/underflow can be input to a-d1 conversion start trigger multijunction timers 10.1 outline of multijunction timers
10 10-5 ver.0.10 multijunction timers 10.1 outline of multijunction timers figure 10.1.1 block diagram of mjt (1/4) note 1: irq0-18 denote interrupt signals, of which the same number indicates the same group of interrupts. (see table 10.1.2.) drq0-13 denote dma request signals fed to the dmac. (see table 10.1.3.) ad0trg and ad1trg denote trigger signals to a-d0 and a-d1 converters, respectively. note 2: indicates timer input pin edge selection output. note 3: indicates input signals from peripheral circuits (ad and sio). irq2 irq12 irq12 irq12 clk en udf top 0 clock bus input event bus clk en udf top 1 clk en udf top 2 clk en udf top 3 output event bus tclk0s to 0 irq9 1/2 internal peripheral clock irq8 clk en udf top 4 clk en udf top 5 tclk0 tin0 tin7 tclk1 s s tin0s clk en udf top 6 clk en udf top 7 s s s irq9 tin1 irq9 tin2 s s clk en udf top 8 clk en udf top 9 clk en udf top 10 clk en/cap udf tio 0 clk en/cap udf tio 1 clk en/cap udf tio 2 clk en/cap udf tio 3 clk en/cap udf tio 4 s s tin3 s s tin4 tin5 s s irq12 tin6 psc1 psc0 clk en/cap udf tio 5 s s irq8 tin8 tclk2 clk en/cap udf tio 6 s s irq8 tin9 clk en/cap udf tio 7 s s irq8 tin10 s s clk en/cap udf tio 8 clk en/cap udf tio 9 irq8 tin11 s s f/f0 f/f1 f/f2 f/f3 f/f4 f/f5 f/f6 f/f7 f/f8 f/f9 f/f10 f/f11 f/f12 f/f13 f/f14 f/f15 s f/f16 f/f17 f/f18 f/f19 f/f20 s : selector f/f : output flip-flop psc0 - 5 : prescaler s s s s s s s s s s s s s s irq2 irq2 irq2 irq2 irq2 to 1 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 to 10 to 11 to 12 to 13 to 14 to 15 irq1 irq1 irq6 irq6 irq5 irq0 irq0 irq0 irq0 irq4 to 16 to 17 to 18 to 19 to 20 irq4 drq0 irq3 irq3 psc2 irq4 irq4 tin1s tin2s tin3s tin4s tin5s tin6s tclk1s tclk2s tin7s tin8s tin9s tin10s tin11s drq7 drq8 drq9 drq10 drq11 ad0trg (to a-d0 converter) 3210 3210 (note 1) 3210 3210 0123 0123
10 10-6 ver.0.10 multijunction timers 10.1 outline of multijunction timers figure 10.1.2 block diagram of mjt (2/4) clk tms 0 s ovf cap3 cap2 cap1 cap0 s s s s tclk3 tclk3s drq3 irq10 tin12 tin13 tin14 tin15 clk tms 1 ovf cap3 cap2 cap1 cap0 s s s s s drq5 tin16 tin17 tin18 tin19 drq6 irq10 irq10 irq10 irq10 irq10 irq10 irq10 clk tml0 cap3 cap2 cap1 cap0 s s s s tin20 tin21 tin22 tin23 irq11 irq11 irq11 irq11 irq7 irq7 tin12s tin13s tin14s tin15s tin16s tin17s tin18s tin19s tin20s tin21s tin22s tin23s s drq12 clk tml1 cap3 cap2 cap1 cap0 s s s s tin30 tin31 tin32 tin33 tin30s tin31s tin32s tin33s s irq18 irq18 irq18 irq18 s : selector 3210 3210 0123 clock bus input event bus output event bus 3210 3210 0123 1/2 internal peripheral clock 1/2 internal peripheral clock
10 10-7 ver.0.10 figure 10.1.3 block diagram of mjt (3/4) multijunction timers 10.1 outline of multijunction timers clk tid0 ovf udf tin24 tin25 irq14 clk tod0_0 udf f/f21 clk tod0_1 udf f/f22 to21 to22 clk tod0_2 udf f/f23 clk tod0_3 udf f/f24 to23 to24 clk tod0_4 udf f/f25 clk tod0_5 udf f/f26 to25 to26 clk tod0_6 udf f/f27 clk tod0_7 udf f/f28 to27 to28 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq13 clk1 clk2 psc3 clk tid1 tin26 tin27 irq15 clk tod1_0 udf f/f29 clk tod1_1 udf f/f30 to29 to30 clk tod1_2 udf f/f31 clk tod1_3 udf f/f32 to31 to32 clk tod1_4 udf f/f33 clk tod1_5 udf f/f34 to33 to34 clk tod1_6 udf f/f35 clk tod1_7 udf f/f36 to35 to36 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 clk1 clk2 psc4 clk tid2 tin28 tin29 clk tom0_0 udf f/f37 clk tom0_1 udf f/f38 to37 to38 clk tom0_2 udf f/f39 clk tom0_3 udf f/f40 to39 to40 clk tom0_4 udf f/f41 clk tom0_5 udf f/f42 to41 to42 clk tom0_6 udf f/f43 clk tom0_7 udf f/f44 to43 to44 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 clk1 clk2 psc5 ovf udf ovf udf (note) irq17 en clock bus input event bus output event bus 3210 3210 0123 1/2 internal peripheral clock 1/2 internal peripheral clock 1/2 internal peripheral clock 3210 3210 s : selector 0123 ad1trg (to a-d1 converter) en en en en en en en en en en en en en en en
10 10-8 ver.0.10 multijunction timers 10.1 outline of multijunction timers figure 10.1.4 block diagram of mjt (4/4) ad0 completed tio8-udf s dma0 udf end dmairq0 s dmairq0 tin13 tin18 s dmairq0 s dmairq0 tin19 sio0-txd sio1-rxd sio0-rxd s dmairq1 dmairq1 sio2-rxd sio1-txd dmairq1 dmairq1 sio2-txd sio3-rxd dmairq1 sio3-txd tin2 tin7 tin8 tin20 tin1 tin0 s dmairq0 s s s s clock bus input event bus output event bus 3210 3210 3210 0123 0123 (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) dma1 udf end dma2 udf end dma3 udf end dma4 udf (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) (note 3) dma5 udf end dma7 udf end dma6 udf end (note 3) (note 3) dma8 udf end dma9 udf 3210
10 10-9 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2 common units of multijunction timer the common units of the multijunction timer include the following: ? prescaler unit ? clock bus/input-output event bus control unit ? input processing control unit ? output flip-flop control unit ? interrupt control unit 10.2.1 timer common register map the diagrams in the next pages show a map of registers in the common units of the multijunction timer.
10 10-10 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.1 timer common register map (1/2) address d0 d7 +0 address +1 address d8 d15 note: the registers included in thick frames must always be accessed in halfwords. h'0080 0200 h'0080 0214 h'0080 0216 h'0080 0218 h'0080 0210 h'0080 0212 h'0080 0224 h'0080 0226 h'0080 0228 h'0080 022a h'0080 0222 h'0080 0236 h'0080 0238 h'0080 023a h'0080 023c h'0080 023e h'0080 0234 h'0080 0204 h'0080 0230 h'0080 0232 h'0080 07d0 h'0080 021a h'0080 0220 blank addresses are reserved. tin input processing control register 0 (tincr0) tin input processing control register 1 (tincr1) clock bus & input event bus control register (ckiebcr) prescaler register 2 (prs2) output event bus control register (oebcr) tin input processing control register 4 (tincr4) f/f protect register 0 (ffp0) f/f data register 0 (ffd0) f/f source select register 1 (ffs1) f/f data register 1 (ffd1) tio interrupt control register 0 (tioir0) tio interrupt control register 1 (tioir1) tod0 control register (tod0cr) prescaler register 0 (prs0) prescaler register 1 (prs1) tclk input processing control register (tclkcr) h'0080 0202 tin input processing control register 2 (tincr2) tin input processing control register 3 (tincr3) f/f source select register 0 (ffs0) f/f protect register 1 (ffp1) top interrupt control register 2 (topir2) top interrupt control register 3 (topir3) top interrupt control register 0 (topir0) top interrupt control register 1 (topir1) tio interrupt control register 2 (tioir2) tms interrupt control register (tmsir) tin interrupt control register 0 (tinir0) tin interrupt control register 1 (tinir1) tin interrupt control register 2 (tinir2) tin interrupt control register 3 (tinir3) tin interrupt control register 4 (tinir4) tin interrupt control register 5 (tinir5) tin interrupt control register 6 (tinir6) tin interrupt control register 7 (tinir7) prescaler register 3 (prs3) tid0 control & prescaler 3 enable register (tid0prs3en) h'0080 07d2 tod0 interrupt mask register (tod0ima) tod0 interrupt status register (tod0ist) h'0080 07d4 f/f protect register 2 (ffp2) h'0080 07d6 f/f data register 2 (ffd2) h'0080 07d8 h'0080 07da h'0080 07dc tod0 enable protect register (tod0pro) h'0080 07de tod0 count enable register (tod0cen) tin input processing control register 3 (tincr3)
10 10-11 ver.0.10 multijunction timers 10.2 common units of multijunction timer address d0 d7 +0 address +1 address d8 d15 note: the re g isters included in thick frames must always be accessed in halfwords. h'0080 0bd0 blank addresses are reserved. prescaler register 4 (prs4) tid1 control & prescaler 4 enable register (tid1prs4en) h'0080 0bd2 tod1 interrupt mask register (tod1ima) tod1 interrupt status register (tod1ist) h'0080 0bd4 f/f protect register 3 (ffp3) h'0080 0bd6 f/f data register 3 (ffd3) h'0080 0cd0 prescaler register 5 (prs5) tid2 control & prescaler 5 enable register (tid2prs5en) h'0080 0cd2 tom0 interrupt mask register (tom0ima) tom0 interrupt status register (tom0ist) h'0080 0cd4 f/f protect register 4 (ffp4) h'0080 0cd6 f/f data register 4 (ffd4) figure 10.2.2 timer common register map (2/2)
10 10-12 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2.2 prescaler unit the prescalers prs0-5 are an 8-bit counter, which generates clocks supplied to each timer (top, tio, tms, tml, tid, tod, and tom) from the divide-by-2 frequency of the internal peripheral clock (10.0 mhz when the internal peripheral clock = 20 mhz). the values of prescaler registers are initialized to h'00 when reset. also, when you rewrite the set value of any prescaler register, the device starts operating with the new value simultaneously when the prescaler underflows. values h'00 to h'ff can be set in the counter registers of prescalers. the prescalers' divide-by ratios are given by the equation below. 1 prescaler divide-by ratio = prescaler set value + 1 n prescaler register 0 (prs0) n prescaler register 1 (prs1) n prescaler register 2 (prs2) n prescaler register 3 (prs3) n prescaler register 4 (prs4) n prescaler register 5 (prs5) d0123456d7 ( d8 9 10 11 12 13 14 d15 ) prs0 - prs5 d bit name function r w 0 - 7 prs0, 2 - 5 sets the prescaler's divide-by value 8 - 15 prs1 prescaler registers 0-2 start counting after reset removal. prescaler registers 3-5 each are activated by setting the tid0 control & prescaler 3 enable register, tid1 control & prescaler 4 enable register, and tid2 control & prescaler 5 enable register to 1 (= count start), upon which they reload the prescaler register value and start counting. for details, refer to section 10.7, "tid (input-related 16-bit timer)."
10 10-13 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2.3 clock bus/input-output event bus control unit (1) clock bus the clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0-3. each timer can use this clock bus signal as clock input signal. the table below lists the signals that can be fed to the clock bus. table 10.2.1 signals that can be fed to each clock bus line clock bus acceptable signal 3 tclk0 input 2 internal prescaler (psc2) or tclk3 input 1 internal prescaler (psc1) 0 internal prescaler (psc0) (2) input event bus the input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0-3. each timer can use this input event bus signal as enable (or capture) signal input. the table below lists the signals that can be fed to the input event bus. table 10.2.2 signals that can be fed to each input event bus line input event bus acceptable signal 3 tin3 input, output event bus 2 or tio7 underflow signal 2 tin0 input, tin2 input or tin4 input 1 tin5 input or tio6 underflow signal 0 tin6 input or tio5 underflow signal
10 10-14 ver.0.10 multijunction timers 10.2 common units of multijunction timer (3) output event bus the output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0-3. output event bus signals are connected to output flip-flops, and can also be connected to other peripheral circuits-output event bus 3 to a-d0 converter, output event bus 0 to dma channel 1, and output event bus 1 to dma channel 2. furthermore, output event bus 2 can be connected to input event bus 3. the table below lists the signals that can be connected to the output event bus. table 10.2.3 signals that can be connected (fed) to each output event bus line output event bus connectable (acceptable) signal (note) 3 top8, tio3, tio4, or tio8 underflow signal 2 top9 or tio2 underflow signal 1 top7 or tio1 underflow signal 0 top6 or tio0 underflow signal note: for details about the output destinations of output event bus signals, refer to figure 10.1.1, "block diagram of mjt." timings at which signals are generated to the output event bus by each timer (and those generated to the input event bus by tio5, 6) are shown below. (note that they are generated at different timings than those forwarded to output flip-flops by timers.) table 10.2.4 timings at which signals are generated to the output event bus by each timer (1/2) timer mode timings at which signals are generated to the output event bus top single-shot output mode when the counter underflows delayed single-shot output mode when the counter underflows continuous output mode when the counter underflows tio (note) measure clear input mode when the counter underflows measure free-run input mode when the counter underflows noise processing input mode when the counter underflows pwm output mode when the counter underflows single-shot output mode when the counter underflows delayed single-shot output mode when the counter underflows continuous output mode when the counter underflows tms (16-bit measure input) no signal generation function tml (32-bit measure input) no signal generation function tid fixed period mode no signal generation function event count mode no signal generation function multiply-by-4 event count mode no signal generation function tod pwm output mode no signal generation function single-shot output mode no signal generation function delayed single-shot output mode no signal generation function continuous output mode no signal generation function note: tio5, 6 output underflow signals to the input event bus.
10 10-15 ver.0.10 multijunction timers 10.2 common units of multijunction timer table 10.2.4 timings at which signals are generated to the output event bus by each timer (2/2) timer mode timings at which signals are generated to the output event bus tom pwm output mode no signal generation function single-shot pwm output mode no signal generation function single-shot output mode no signal generation function continuous output mode no signal generation function figure 10.2.3 conceptual diagram of the clock bus and input/output event bus tclk0s tclk0 tin0 tin2 tin3 tin4 tin5 tin6 psc1 psc0 psc2 tclk3 udf tio 5 udf tio 6 s udf tio 7 udf top 6 udf top 7 udf top 8 udf top 9 udf tio 0 udf tio 1 udf tio 2 udf tio 3 udf tio 4 udf tio 8 tclk3s tin0s tin2s tin3s tin4s tin5s tin6s clock bus input event bus output event bus s : selector psc0 - 2 : prescaler 3210 3210 3210 3210 0123 0123 1/2 internal peripheral clock
10 10-16 ver.0.10 multijunction timers 10.2 common units of multijunction timer the clock bus/input-output bus control unit has the following registers: ? clock bus & input event bus control register (ckiebcr) ? output event bus control register (oebcr) n clock bus & input event bus control register (ckiebcr) d8 9 1011121314d15 ieb3s ieb2s ieb1s ieb0s ckb2s d bit name function r w 8, 9 ieb3s 0x : selects external input 3 (tin3) (input event bus 3 input selection) 10 : selects output event bus 2 11 : selects tio7 output 10, 11 ieb2s 00 : selects external input 0 (tin0) (input event bus 2 input selection) 01 : selects external input 2 (tin2) 1x : selects external input 4 (tin4) 12 ieb1s 0 : selects external input 5 (tin5) (input event bus 1 input selection) 1 : selects tio6 output 13 ieb0s 0 : selects external input 6 (tin6) (input event bus 0 input selection) 1 : selects tio5 output 14 no functions assigned 0 15 ckb2s 0 : selects prescaler 2 (clock bus 2 input selection) 1 : selects external clock 3 (tclk3) the register ckiebcr is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus.
10 10-17 ver.0.10 multijunction timers 10.2 common units of multijunction timer n output event bus control register (oebcr) d8 9 1011121314d15 oeb3s oeb2s oeb1s oeb0s d bit name function r w 8, 9 oeb3s 00 : selects top8 output (output event bus 3 input selection) 01 : selects tio3 output 10 : selects tio4 output 11 : selects tio8 output 10 no functions assigned 0 11 oeb2s 0 : selects top9 output (output event bus 2 input selection) 1 : selects tio2 output 12 no functions assigned 0 13 oeb1s 0 : selects top7 output (output event bus 1 input selection) 1 : selects tio1 output 14 no functions assigned 0 15 oeb0s 0 : selects top6 output (output event bus 0 input selection) 1 : selects tio0 output the register oebcr is used to select the timer (top or tio) whose underflow signal is supplied to the output event bus.
10 10-18 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2.4 input processing control unit the input processing control unit processes the tclk and tin signals fed into the mjt. in the tclk input processing unit, selection is made of the source of tclk signal, or for external input, the active edge (rising or falling or both) or level (high or low) of the signal, with or at which to generate the clock signal fed to the clock bus. in the tin input processing unit, selection is made of the active edge (rising or falling or both) or level (high or low) of the signal at which to generate the enable, measure or count source signal for each timer or the signal fed to each event bus. following input processing control registers are included: ? tclk input processing control register (tclkcr) ? tin input processing control register 0 (tincr0) ? tin input processing control register 1 (tincr1) ? tin input processing control register 2 (tincr2) ? tin input processing control register 3 (tincr3) ? tin input processing control register 4 (tincr4)
10 10-19 ver.0.10 multijunction timers 10.2 common units of multijunction timer (1) functions of tclk input processing control registers item function 1/2 internal peripheral clock rising clock edge falling clock edge both edges low level high level count clock 1/2 internal peripheral clock tclk count clock tclk count clock tclk count clock tclk count clock 1/2 internal peripheral clock tclk count clock 1/2 internal peripheral clock
10 10-20 ver.0.10 multijunction timers 10.2 common units of multijunction timer (2) functions of tin input processing control registers item function rising edge falling edge both edges low level high level tin internal edge signal tin internal edge signal tin internal ed g e si g nal tclk psc x clock width or tclk x input internal edge signal tin internal edge signal psc x clock width or tclk x input
10 10-21 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 tclk3s tclk2s tclk1s tclk0s d bit name function r w 0, 1 no functions assigned 0 2, 3 tclk3s 00 : 1/2 internal peripheral clock (tclk3 input 01 : rising edge processing selection) 10 : falling edge 11 : both edges 4 no functions assigned 0 5 - 7 tclk2s 000 : invalidates input (tclk2 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 8 no functions assigned 0 9 - 11 tclk1s 000 : invalidates input (tclk1 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 12, 13 no functions assigned 0 14, 15 tclk0s 00 : 1/2 internal peripheral clock (tclk0 input 01 : rising edge processing selection) 10 : falling edge 11 : both edges note: this register must always be accessed in halfwords. n tlck input processing control register (tclkcr)
10 10-22 ver.0.10 multijunction timers 10.2 common units of multijunction timer d01234567891011121314d15 tin4s tin3s tin2s tin1s tin0s d bit name function r w 0 no functions assigned 0 1 - 3 tin4s 000 : invalidates input (tin4 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 4 no functions assigned 0 5 - 7 tin3s 000 : invalidates input (tin3 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 8, 9 no functions assigned 0 10, 11 tin2s 00 : invalidates input (tin2 input 01 : rising edge processing selection) 10 : falling edge 11 : both edges 12, 13 tin1s 00 : invalidates input (tin1 input 01 : rising edge processing selection) 10 : falling edge 11 : both edges 14, 15 tin0s 00 : invalidates input (tin0 input 01 : rising edge processing selection) 10 : falling edge 11 : both edges note: this register must always be accessed in halfwords. n tin input processing control register 0 (tincr0)
10 10-23 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 tin8s tin7s tin6s tin5s d bit name function r w 0 no functions assigned 0 1 - 3 tin8s 000 : invalidates input (tin8 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 4 no functions assigned 0 5 - 7 tin7s 000 : invalidates input (tin7 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 8 no functions assigned 0 9 - 11 tin6s 000 : invalidates input (tin6 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 12 no functions assigned 0 13 - 15 tin5s 000 : invalidates input (tin5 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level note: this register must always be accessed in halfwords. n tin input processing control register 1 (tincr1)
10 10-24 ver.0.10 multijunction timers 10.2 common units of multijunction timer d01234567891011121314d15 tin11s tin10s tin9s d bit name function r w 0 - 4 no functions assigned 0 5 - 7 tin11s 000 : invalidates input (tin11 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 8 no functions assigned 0 9 - 11 tin10s 000 : invalidates input (tin10 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level 12 no functions assigned 0 13 - 15 tin9s 000 : invalidates input (tin9 input 001 : rising edge processing selection) 010 : falling edge 011 : both edges 10x : low level 11x : high level note: this register must always be accessed in halfwords. n tin input processing control register 2 (tincr2)
10 10-25 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 tin19s tin18s tin17s tin16s tin15s tin14s tin13s tin12s d bit name function r w 0, 1 tin19s (tin19 input processing selection) 00 : invalidates input 2, 3 tin18s (tin18 input processing selection) 01 : rising edge 4, 5 tin17s (tin17 input processing selection) 10 : falling edge 6, 7 tin16s (tin16 input processing selection) 11 : both edges 8, 9 tin15s (tin15 input processing selection) 10, 11 tin14s (tin14 input processing selection) 12, 13 tin13s (tin13 input processing selection) 14, 15 tin12s (tin12 input processing selection) note: this register must always be accessed in halfwords. n tin input processing control register 4 (tincr4) n tin input processing control register 3 (tincr3) d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 tin33s tin32s tin31s tin30s tin23s tin22s tin21s tin20s d bit name function r w 0, 1 tin33s (tin33 input processing selection) 00 : invalidates input 2, 3 tin32s (tin32 input processing selection) 01 : rising edge 4, 5 tin31s (tin31 input processing selection) 10 : falling edge 6, 7 tin30s (tin30 input processing selection) 11 : both edges 8, 9 tin23s (tin23 input processing selection) 10, 11 tin22s (tin22 input processing selection) 12, 13 tin21s (tin21 input processing selection) 14, 15 tin20s (tin20 input processing selection) note: this register must always be accessed in halfwords.
10 10-26 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2.5 output flip-flop control unit the output flip-flop control unit controls the flip-flop (f/f) provided for each timer output. following flip-flop control registers are included: ? f/f source select register 0 (ffs0) ? f/f source select register 1 (ffs1) ? f/f protect register 0 (ffp0) ? f/f protect register 1 (ffp1) ? f/f protect register 2 (ffp2) ? f/f protect register 3 (ffp3) ? f/f protect register 4 (ffp4) ? f/f data register 0 (ffd0) ? f/f data register 1 (ffd1) ? f/f data register 2 (ffd2) ? f/f data register 3 (ffd3) ? f/f data register 4 (ffd4) timings at which signals are generated to the output flip-flop by each timer are shown in table 10.2.5 below. (note that signals are generated at different timings than those fed to the output event bus.)
10 10-27 ver.0.10 multijunction timers 10.2 common units of multijunction timer table 10.2.5 timings at which signals are generated to the output flip-flop by each timer timer mode timings at which signals are generated to the output flip-flop top single-shot output mode when counter is enabled and when underflows delayed single-shot output mode when counter underflows continuous output mode when counter is enabled and when underflows tio measure clear input mode when counter underflows measure free-run input mode when counter underflows noise processing input mode when counter underflows pwm output mode when counter is enabled and when underflows single-shot output mode when counter is enabled and when underflows delayed single-shot output mode when counter underflows continuous output mode when counter is enabled and when underflows tms (16-bit measure input) no signal generation function tml (32-bit measure input) no signal generation function tid fixed period count mode no signal generation function event count mode no signal generation function multiply-by-4 event count mode no signal generation function tod pwm output mode when counter is enabled and when underflows single-shot output mode when counter is enabled and when underflows delayed single-shot output mode when counter underflows continuous output mode when counter is enabled and when underflows tom pwm output mode when counter is enabled and when underflows single-shot pwm output mode when counter underflows single-shot output mode when counter is enabled and when underflows continuous output mode when counter is enabled and when underflows
10 10-28 ver.0.10 figure 10.2.4 configuration of the f/f output circuit multijunction timers 10.2 common units of multijunction timer output event bus 0 dn f/f protect (fpn) wr dn output control (on/off) ton internal edge signal port operation mode register(pnmod) f/fn output data (fdn) top tio tod tom udf f/f source selection (ffn) output event bus 1 output event bus 2 output event bus 3 note: dn denotes the data bus. f/f f/f f/f
10 10-29 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 ff15 ff14 ff13 ff12 ff11 ff10 ff9 ff8 ff7 ff6 d bit name function r w 0 - 2 no functions assigned 0 3 ff15 (f/f15 source selection) 0 : tio4 output 1 : output event bus 0 4 ff14 (f/f14 source selection) 0 : tio3 output 1 : output event bus 0 5 ff13 (f/f13 source selection) 0 : tio2 output 1 : output event bus 3 6 ff12 (f/f12 source selection) 0 : tio1 output 1 : output event bus 2 7 ff11 (f/f11 source selection) 0 : tio0 output 1 : output event bus 1 8, 9 ff10 (f/f10 source selection) 0x : top10 output 10 : output event bus 0 11 : output event bus 1 10, 11 ff9 (f/f9 source selection) 0x : top9 output 10 : output event bus 0 11 : output event bus 1 12, 13 ff8 (f/f8 source selection) 00 : top8 output 01 : output event bus 0 10 : output event bus 1 11 : output event bus 2 14 ff7 (f/f7 source selection) 0 : top7 output 1 : output event bus 0 15 ff6 (f/f6 source selection) 0 : top6 output 1 : output event bus 1 note: this register must always be accessed in halfwords. n f/f source select register 0 (ffs0)
10 10-30 ver.0.10 multijunction timers 10.2 common units of multijunction timer n f/f source select register 1 (ffs1) d8 9 1011121314d15 ff19 ff18 ff17 ff16 d bit name function r w 8, 9 ff19 (f/f19 source selection) 0x : tio8 output 10 : output event bus 0 11 : output event bus 1 10, 11 ff18 (f/f18 source selection) 0x : tio7 output 10 : output event bus 0 11 : output event bus 1 12, 13 ff17 (f/f17 source selection) 0x : tio6 output 10 : output event bus 0 11 : output event bus 1 14, 15 ff16 (f/f16 source selection) 00 : tio5 output 01 : output event bus 0 10 : output event bus 1 11 : output event bus 3 the registers ffs0 and ffs1 are used to select the signal sources fed to each output f/f (flip- flop). for these signal sources, you can choose signals from the internal output bus or underflow output from each timer.
10 10-31 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 d bit name function r w 0 fp15 (f/f15 protect) 0 : enables write to f/f output bit 1 fp14 (f/f14 protect) 1 : disables write to f/f output bit 2 fp13 (f/f13 protect) 3 fp12 (f/f12 protect) 4 fp11 (f/f11 protect) 5 fp10 (f/f10 protect) 6 fp9 (f/f9 protect) 7 fp8 (f/f8 protect) 8 fp7 (f/f7 protect) 9 fp6 (f/f6 protect) 10 fp5 (f/f5 protect) 11 fp4 (f/f4 protect) 12 fp3 (f/f3 protect) 13 fp2 (f/f2 protect) 14 fp1 (f/f1 protect) 15 fp0 (f/f0 protect) note: this register must always be accessed in halfwords. this register controls write to each output f/f (flip-flop) by enabling or disabling it. when this register is set to disable write to any output f/f, writing to the f/f data register has no effect. n f/f protect register 0 (ffp0)
10 10-32 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 fp20 fp19 fp18 fp17 fp16 d bit name function r w 8 - 10 no functions assigned 0 11 fp20 (f/f20 protect) 0 : enables write to f/f output bit 12 fp19 (f/f19 protect) 1 : disables write to f/f output bit 13 fp18 (f/f18 protect) 14 fp17 (f/f17 protect) 15 fp16 (f/f16 protect) n f/f protect register 2 (ffp2) n f/f protect register 1 (ffp1) d8 9 1011121314d15 fp21 fp22 fp23 fp24 fp25 fp26 fp27 fp28 d bit name function r w 8 fp21 (f/f21 protect) 0 : enables write to f/f output bit 9 fp22 (f/f22 protect) 1 : disables write to f/f output bit 10 fp23 (f/f23 protect) 11 fp24 (f/f24 protect) 12 fp25 (f/f25 protect) 13 fp26 (f/f26 protect) 14 fp27 (f/f27 protect) 15 fp28 (f/f28 protect) this register controls write to each output f/f (flip-flop) by enabling or disabling it. when this register is set to disable write to any output f/f, writing to the f/f data register has no effect.
10 10-33 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 fp29 fp30 fp31 fp32 fp33 fp34 fp35 fp36 d bit name function r w 8 fp29 (f/f29 protect) 0 : enables write to f/f output bit 9 fp30 (f/f30 protect) 1 : disables write to f/f output bit 10 fp31 (f/f31 protect) 11 fp32 (f/f32 protect) 12 fp33 (f/f33 protect) 13 fp34 (f/f34 protect) 14 fp35 (f/f35 protect) 15 fp36 (f/f36 protect) n f/f protect register 4 (ffp4) n f/f protect register 3 (ffp3) d8 9 1011121314d15 fp37 fp38 fp39 fp40 fp41 fp42 fp43 fp44 d bit name function r w 8 fp37 (f/f37 protect) 0 : enables write to f/f output bit 9 fp38 (f/f38 protect) 1 : disables write to f/f output bit 10 fp39 (f/f39 protect) 11 fp40 (f/f40 protect) 12 fp41 (f/f41 protect) 13 fp42 (f/f42 protect) 14 fp43 (f/f43 protect) 15 fp44 (f/f44 protect) this register controls write to each output f/f (flip-flop) by enabling or disabling it. when this register is set to disable write to any output f/f, writing to the f/f data register has no effect.
10 10-34 ver.0.10 multijunction timers 10.2 common units of multijunction timer d01234567891011121314d15 fd15 fd14 fd13 fd12 fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 d bit name function r w 0 fd15 (f/f15 output data) 0 : f/f output data = 0 1 fd14 (f/f14 output data) 1 : f/f output data = 1 2 fd13 (f/f13 output data) 3 fd12 (f/f12 output data) 4 fd11 (f/f11 output data) 5 fd10 (f/f10 output data) 6 fd9 (f/f9 output data) 7 fd8 (f/f8 output data) 8 fd7 (f/f7 output data) 9 fd6 (f/f6 output data) 10 fd5 (f/f5 output data) 11 fd4 (f/f4 output data) 12 fd3 (f/f3 output data) 13 fd2 (f/f2 output data) 14 fd1 (f/f1 output data) 15 fd0 (f/f0 output data) note: this register must always be accessed in halfwords. this register is used to set data in each output f/f (flip-flop). normally, the data output from f/f changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any f/f. the f/f data register can only be accessed for write when the f/f protect register described above is enabled for write. n f/f data register 0 (ffd0)
10 10-35 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 fd20 fd19 fd18 fd17 fd16 d bit name function r w 8 - 10 no functions assigned 0 11 fd20 (f/f20 output data) 0 : f/f output data = 0 12 fd19 (f/f19 output data) 1 : f/f output data = 1 13 fd18 (f/f18 output data) 14 fd17 (f/f17 output data) 15 fd16 (f/f16 output data) n f/f data register 2 (ffd2) n f/f data register 1 (ffd1) d8 9 1011121314d15 fd21 fd22 fd23 fd24 fd25 fd26 fd27 fd28 d bit name function r w 8 fd21 (f/f21 output data) 0 : f/f output data = 0 9 fd22 (f/f22 output data) 1 : f/f output data = 1 10 fd23 (f/f23 output data) 11 fd24 (f/f24 output data) 12 fd25 (f/f25 output data) 13 fd26 (f/f26 output data) 14 fd27 (f/f27 output data) 15 fd28 (f/f28 output data) this register is used to set data in each output f/f (flip-flop). normally, the data output from f/f changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any f/f. the f/f data register can only be accessed for write when the f/f protect register described above is enabled for write.
10 10-36 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 fd29 fd30 fd31 fd32 fd33 fd34 fd35 fd36 d bit name function r w 8 fd29 (f/f29 output data) 0 : f/f output data = 0 9 fd30 (f/f30 output data) 1 : f/f output data = 1 10 fd31 (f/f31 output data) 11 fd32 (f/f32 output data) 12 fd33 (f/f33 output data) 13 fd34 (f/f34 output data) 14 fd35 (f/f35 output data) 15 fd36 (f/f36 output data) n f/f data register 4 (ffd4) n f/f data register 3 (ffd3) d8 9 1011121314d15 fd37 fd38 fd39 fd40 fd41 fd42 fd43 fd44 d bit name function r w 8 fd37 (f/f37 output data) 0 : f/f output data = 0 9 fd38 (f/f38 output data) 1 : f/f output data = 1 10 fd39 (f/f39 output data) 11 fd40 (f/f40 output data) 12 fd41 (f/f41 output data) 13 fd42 (f/f42 output data) 14 fd43 (f/f43 output data) 15 fd44 (f/f44 output data) this register is used to set data in each output f/f (flip-flop). normally, the data output from f/f changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any f/f. the f/f data register can only be accessed for write when the f/f protect register described above is enabled for write.
10 10-37 ver.0.10 multijunction timers 10.2 common units of multijunction timer 10.2.6 interrupt control unit the interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer. following 22 timer interrupt control registers are provided for each timer. ? top interrupt control register 0 (topir0) ? top interrupt control register 1 (topir1) ? top interrupt control register 2 (topir2) ? top interrupt control register 3 (topir3) ? tio interrupt control register 0 (tioir0) ? tio interrupt control register 1 (tioir1) ? tio interrupt control register 2 (tioir2) ? tms interrupt control register (tmsir) ? tin interrupt control register 0 (tinir0) ? tin interrupt control register 1 (tinir1) ? tin interrupt control register 2 (tinir2) ? tin interrupt control register 3 (tinir3) ? tin interrupt control register 4 (tinir4) ? tin interrupt control register 5 (tinir5) ? tin interrupt control register 6 (tinir6) ? tin interrupt control register 7 (tinir7) ? tod0 interrupt mask register (tod0ima) ? tod0 interrupt status register (tod0ist) ? tod1 interrupt mask register (tod1ima) ? tod1 interrupt status register (tod1ist) ? tom0 interrupt mask register (tom0ima) ? tom0 interrupt status register (tom0ist) for interrupts which have only one source of interrupt in one interrupt table, no interrupt control registers are provided in the timer, and the interrupt status flags are automatically managed within the interrupt controller. for details, refer to chapter 14, "interrupt controller." ? top10 mjt output interrupt 5 (irq5) ? tid0 tid0 output interrupt (irq14) ? tid1 tid1 output interrupt (irq15) ? tid2 tid2 output interrupt (irq17)
10 10-38 ver.0.10 multijunction timers 10.2 common units of multijunction timer for interrupts which have two or more sources of interrupt in one interrupt table, interrupt control registers are provided, with which to control interrupt requests and determine interrupt input. therefore, the status flags in the interrupt controller function only as a bit to show whether an interrupt-enabled interrupt request occurred and cannot be written to. (1) interrupt request status bit this status bit shows whether an interrupt request occurred. when an interrupt request is generated, this bit is set in hardware (but cannot be set in software). the status bit is cleared by writing a 0, but not affected by writing a 1, in which case the bit holds the status intact. because the status bit is unaffected by interrupt mask bits, it can also be used to check the operation of peripheral function. in interrupt processing, make sure that among grouped interrupt flags, only the flag for the serviced interrupt is cleared. clearing flags for unserviced interrupts results in the pending interrupt requests also being cleared. (2) interrupt mask bit this bit is used to disable unnecessary interrupts among grouped interrupt requests. set this bit to 0 to enable interrupts or 1 to disable interrupts. figure 10.2.5 interrupt status register and mask register interrupt controller each timer or tin input interrupt request interrupt status data bus set group interrupt interrupt enable clear f/f f/f data = 0
10 10-39 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.6 example for clearing the interrupt status b4 5 6 b7 interrupt status flag initial state b6 event occurred interrupt request b4 event occurred only b6 cleared b4 data retained b4 5 6 b7 1 101 write to the interrupt status example for clearing the interrupt status 0 000 0 010 0 110 0 100
10 10-40 ver.0.10 multijunction timers 10.2 common units of multijunction timer the table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller. table 10.2.6 interrupt signals generated by mjt signal name source of interrupt generated interrupt sources input to icu (note 1) number of input sources irq0 tio0, tio1, tio2, tio3 mjt output interrupt 0 4 irq1 top6, top7 mjt output interrupt 1 2 irq2 top0, top1, top2, top3, top4, top5 mjt output interrupt 2 6 irq3 tio8, tio9 mjt output interrupt 3 2 irq4 tio4, tio5, tio6, tio7 mjt output interrupt 4 4 irq6 top8, top9 mjt output interrupt 6 2 irq7 tms0, tms1 mjt output interrupt 7 2 irq8 tin7, tin8, tin9, tin10, tin11 mjt input interrupt 0 5 irq9 tin0, tin1, tin2 mjt input interrupt 1 3 irq10 tin12, tin13, tin14, tin15, tin16, mjt input interrupt 2 8 tin17, tin18, tin19 irq11 tin20, tin21, tin22, tin23 mjt input interrupt 3 4 irq12 tin3, tin4, tin5, tin6 mjt input interrupt 4 4 irq13 tod0_0, tod0_1, tod0_2, tod0_3, tod0 output interrupt 8 tod0_4, tod0_5, tod0_6, tod0_7 irq16 tod1_0, tod1_1, tod1_2, tod1_3, tod1 + tom0 output interrupt 16 tod1_4, tod1_5, tod1_6, tod1_7, tom0_0, tom0_1, tom0_2, tom0_3, tom0_4, tom0_5, tom0_6, tom0_7 irq18 tin30, tin31, tin32, tin33 tml1 input interrupt 4 note 1: refer to chapter 5, "interrupt controller (icu)." note 2: for top10 and tid0-2, there are no interrupt status and mask bits in mjt interrupt control registers because they only have one source of interrupt in the group. (they are controlled directly by the interrupt controller.)
10 10-41 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 topis5 topis4 topis3 topis2 topis1 topis0 d bit name function r w 0, 1 no functions assigned 0 2 topis5 (top5 interrupt status) 0 : no interrupt request 3 topis4 (top4 interrupt status) 1 : interrupt request generated 4 topis3 (top3 interrupt status) 5 topis2 (top2 interrupt status) 6 topis1 (top1 interrupt status) 7 topis0 (top0 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n top interrupt control register 1 (topir1) n top interrupt control register 0 (topir0) d8 9 1011121314d15 topim5 topim4 topim3 topim2 topim1 topim0 d bit name function r w 8, 9 no functions assigned 0 10 topim5 (top5 interrupt mask) 0 : enables interrupt request 11 topim4 (top4 interrupt mask) 1 : masks (disables) interrupt request 12 topim3 (top3 interrupt mask) 13 topim2 (top2 interrupt mask) 14 topim1 (top1 interrupt mask) 15 topim0 (top0 interrupt mask)
10 10-42 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.7 block diagram of mjt output interrupt 2 mjt output interrupt 2 irq2 data bus b2 topis5 f/f topim5 f/f b10 b3 topis4 f/f topim4 f/f b11 b4 topis3 f/f topim3 f/f b12 b5 topis2 f/f topim2 f/f b13 b6 topis1 f/f topim1 f/f b14 b7 topis0 f/f topim0 f/f b15 (level) 6-source inputs topir0 topir1 top5udf top4udf top3udf top2udf top1udf top0udf
10 10-43 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 topis7 topis6 topim7 topim6 d bit name function r w 0, 1 no functions assigned 0 2 topis7 (top7 interrupt status) 0 : no interrupt request 3 topis6 (top6 interrupt status) 1 : interrupt request generated 4, 5 no functions assigned 0 6 topim7 (top7 interrupt mask) 0 : enables interrupt request 7 topim6 (top6 interrupt mask) 1 : masks (disables) interrupt request w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n top interrupt control register 2 (topir2) figure 10.2.8 block diagram of mjt output interrupt 1 b2 topis7 f/f topim7 f/f b6 b3 topis6 f/f topim6 f/f b7 topir2 top7udf top6udf data bus mjt output interrupt 1 irq1 (level) 2-source inputs
10 10-44 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 topis9 topis8 topim9 topim8 d bit name function r w 8, 9 no functions assigned 0 10 topis9 (top9 interrupt status) 0 : no interrupt request 11 topis8 (top8 interrupt status) 1 : interrupt request generated 12, 13 no functions assigned 0 14 topim9 (top9 interrupt mask) 0 : enables interrupt request 15 topim8 (top8 interrupt mask) 1 : masks (disables) interrupt request w = : only writing a 0 is effective; when you write a 1, the previous value is retained. note: for top10, there are no interrupt status and mask bits in mjt interrupt control registers because it only has one source of interrupt in the group. (it is controlled directly by the interrupt controller.) n top interrupt control register 3 (topir3) figure 10.2.9 block diagram of mjt output interrupt 6 b10 topis9 f/f topim9 f/f b14 b11 topis8 f/f topim8 f/f b15 topir3 top9udf top8udf data bus mjt output interrupt 6 irq6 (level) 2-source inputs
10 10-45 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tiois3 tiois2 tiois1 tiois0 tioim3 tioim2 tioim1 tioim0 d bit name function r w 0 tiois3 (tio3 interrupt status) 0 : no interrupt request 1 tiois2 (tio2 interrupt status) 1 : interrupt request generated 2 tiois1 (tio1 interrupt status) 3 tiois0 (tio0 interrupt status) 4 tioim3 (tio3 interrupt mask) 0 : enables interrupt request 5 tioim2 (tio2 interrupt mask) 1 : masks (disables) interrupt request 6 tioim1 (tio1 interrupt mask) 7 tioim0 (tio0 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tio interrupt control register 0 (tioir0) figure 10.2.10 block diagram of mjt output interrupt 0 b0 tiois3 f/f tioim3 f/f b4 b1 tiois2 f/f tioim2 f/f b5 b2 tiois1 f/f tioim1 f/f b6 b3 tiois0 f/f tioim0 f/f b7 tioir0 tio3udf tio2udf tio1udf tio0udf data bus mjt output interrupt 0 irq0 (level) 4-source inputs
10 10-46 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 tiois7 tiois6 tiois5 tiois4 tioim7 tioim6 tioim5 tioim4 d bit name function r w 8 tiois7 (tio7 interrupt status) 0 : no interrupt request 9 tiois6 (tio6 interrupt status) 1 : interrupt request generated 10 tiois5 (tio5 interrupt status) 11 tiois4 (tio4 interrupt status) 12 tioim7 (tio7 interrupt mask) 0 : enables interrupt request 13 tioim6 (tio6 interrupt mask) 1 : masks (disables) interrupt request 14 tioim5 (tio5 interrupt mask) 15 tioim4 (tio4 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tio interrupt control register 1 (tioir1) figure 10.2.11 block diagram of mjt output interrupt 4 b8 tiois7 f/f tioim7 f/f b12 b9 tiois6 f/f tioim26 f/f b13 b10 tiois5 f/f tioim5 f/f b14 b11 tiois4 f/f tioim4 f/f b15 tioir1 tio7udf tio6udf tio5udf tio4udf data bus mjt output interrupt 4 irq4 (level) 4-source inputs
10 10-47 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tiois9 tiois8 tioim9 tioim8 d bit name function r w 0, 1 no functions assigned 0 2 tiois9 (tio9 interrupt status) 0 : no interrupt request 3 tiois8 (tio8 interrupt status) 1 : interrupt request generated 4, 5 no functions assigned 0 6 tioim9 (tio9 interrupt mask) 0 : enables interrupt request 7 tioim8 (tio8 interrupt mask) 1 : masks (disables) interrupt request w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tio interrupt control register 2 (tioir2) figure 10.2.12 block diagram of mjt output interrupt 3 b2 tiois9 f/f tioim9 f/f b6 b3 tiois8 f/f tioim8 f/f b7 tioir2 tio9udf tio8udf data bus mjt output interrupt 3 irq3 (level) 2-source inputs
10 10-48 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 tmsis1 tmsis0 tmsim1 tmsim0 d bit name function r w 8, 9 no functions assigned 0 10 tmsis1 (tms1 interrupt status) 0 : no interrupt request 11 tmsis0 (tms0 interrupt status) 1 : interrupt request generated 12, 13 no functions assigned 0 14 tmsim1 (tms1 interrupt mask) 0 : enables interrupt request 15 tmsim0 (tms0 interrupt mask) 1 : masks (disables) interrupt request w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tms interrupt control register (tmsir) figure 10.2.13 block diagram of mjt output interrupt 7 b10 tmsis1 f/f tmsim1 f/f b14 b11 tmsis0 f/f tmsim0 f/f b15 tmsir tms1ovf tms0ovf data bus mjt output interrupt 7 irq7 (level) 2-source inputs
10 10-49 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tinis2 tinis1 tinis0 tinim2 tinim1 tinim0 d bit name function r w 0 no functions assigned 0 1 tinis2 (tin2 interrupt status) 0 : no interrupt request 2 tinis1 (tin1 interrupt status) 1 : interrupt request generated 3 tinis0 (tin0 interrupt status) 4 no functions assigned 0 5 tinim2 (tin2 interrupt mask) 0 : enables interrupt request 6 tinim1 (tin1 interrupt mask) 1 : masks (disables) interrupt request 7 tinim0 (tin0 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tin interrupt control register 0 (tinir0) figure 10.2.14 block diagram of mjt input interrupt 1 b1 tinis2 f/f tinim2 f/f b5 b2 tinis1 f/f tinim1 f/f b6 b3 tinis0 f/f tinim0 f/f b7 tinir0 tin2edge tin1edge tin0edge data bus mjt input interrupt 1 irq9 (level) 3-source inputs
10 10-50 ver.0.10 multijunction timers 10.2 common units of multijunction timer d8 9 1011121314d15 tinis6 tinis5 tinis4 tinis3 tinim6 tinim5 tinim4 tinim3 d bit name function r w 8 tinis6 (tin6 interrupt status) 0 : no interrupt request 9 tinis5 (tin5 interrupt status) 1 : interrupt request generated 10 tinis4 (tin4 interrupt status) 11 tinis3 (tin3 interrupt status) 12 tinim6 (tin6 interrupt mask) 0 : enables interrupt request 13 tinim5 (tin5 interrupt mask) 1 : masks (disables) interrupt request 14 tinim4 (tin4 interrupt mask) 15 tinim3 (tin3 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tin interrupt control register 1 (tinir1) figure 10.2.15 block diagram of mjt input interrupt 4 b8 tinis6 f/f tinim6 f/f b12 b9 tinis5 f/f tinim5 f/f b13 b10 tinis4 f/f tinim4 f/f b14 tinir1 tin6edge tin5edge tin4edge b11 tinis3 f/f tinim3 f/f b15 tin3edge data bus mjt input interrupt 4 irq2 (level) 4-source inputs
10 10-51 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tinis11 tinis10 tinis9 tinis8 tinis7 d bit name function r w 0,1,2 no functions assigned 0 3 tinis11 (tin11 interrupt status) 0 : no interrupt request 4 tinis10 (tin10 interrupt status) 1 : interrupt request generated 5 tinis9 (tin9 interrupt status) 6 tinis8 (tin8 interrupt status) 7 tinis7 (tin7 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tin interrupt control register 3 (tinir3) n tin interrupt control register 2 (tinir2) d8 9 1011121314d15 tinim11 tinim10 tinim9 tinim8 tinim7 d bit name function r w 8,9,10 no functions assigned 0 11 tinim11 (tin11 interrupt mask) 0 : enables interrupt request 12 tinim10 (tin10 interrupt mask) 1 : masks (disables) interrupt request 13 tinim9 (tin9 interrupt mask) 14 tinim8 (tin8 interrupt mask) 15 tinim7 (tin7 interrupt mask)
10 10-52 ver.0.10 figure 10.2.16 block diagram of mjt input interrupt 0 multijunction timers 10.2 common units of multijunction timer b3 tinis11 f/f tinim11 f/f b11 b4 tinis10 f/f tinim4 f/f b12 b5 tinis9 f/f tinim9 f/f b13 b6 tinis8 f/f tinim8 f/f b14 b7 tinis7 f/f tinim7 f/f b15 tinir2 tinir3 tin11edge tin10edge tin9edge tin8edge tin7edge data bus mjt input interrupt 0 irq8 (level) 5-source inputs
10 10-53 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tinis19 tinis18 tinis17 tinis16 tinis15 tinis14 tinis13 tinis12 d bit name function r w 0 tinis19 (tin19 interrupt status) 0 : no interrupt request 1 tinis18 (tin18 interrupt status) 1 : interrupt request generated 2 tinis17 (tin17 interrupt status) 3 tinis16 (tin16 interrupt status) 4 tinis15 (tin15 interrupt status) 5 tinis14 (tin14 interrupt status) 6 tinis13 (tin13 interrupt status) 7 tinis12 (tin12 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. n tin interrupt control register 5 (tinir5) n tin interrupt control register 4 (tinir4) d8 9 1011121314d15 tinim19 tinim18 tinim17 tinim16 tinim15 tinim14 tinim13 tinim12 d bit name function r w 8 tinim19 (tin19 interrupt mask) 0 : enables interrupt request 9 tinim18 (tin18 interrupt mask) 1 : masks (disables) interrupt request 10 tinim17 (tin17 interrupt mask) 11 tinim16 (tin16 interrupt mask) 12 tinim15 (tin15 interrupt mask) 13 tinim14 (tin14 interrupt mask) 14 tinim13 (tin13 interrupt mask) 15 tinim12 (tin12 interrupt mask)
10 10-54 ver.0.10 figure 10.2.17 block diagram of mjt input interrupt 2 multijunction timers 10.2 common units of multijunction timer b0 tinis19 f/f tinim19 f/f b8 b1 tinis18 f/f tinim18 f/f b9 b2 tinis17 f/f tinim17 f/f b10 b3 tinis16 f/f tinim16 f/f b11 b4 tinis15 f/f tinim15 f/f b12 tinir4 tinir5 tin19edge tin18edge tin17edge tin16edge tin15edge b5 tinis14 f/f tinim14 f/f b13 b6 tinis13 f/f tinim13 f/f b14 b7 tinis12 f/f tinim12 f/f b15 tin14edge tin13edge tin12edge data bus mjt input interrupt 2 irq10 (level) 8-source inputs
10 10-55 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tinis23 tinis22 tinis21 tinis20 tinim23 tinim22 tinim21 tinim20 d bit name function r w 0 tinis23 (tin23 interrupt status) 0 : no interrupt request 1 tinis22 (tin22 interrupt status) 1 : interrupt request generated 2 tinis21 (tin21 interrupt status) 3 tinis20 (tin20 interrupt status) 4 tinim23 (tin23 interrupt mask) 0 : enables interrupt request 5 tinim22 (tin22 interrupt mask) 1 : masks (disables) interrupt request 6 tinim21 (tin21 interrupt mask) 7 tinim20 (tin20 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. figure 10.2.18 block diagram of mjt input interrupt 3 n tin interrupt control register 6 (tinir6) b0 tinis23 f/f tinim23 f/f b4 b1 tinis22 f/f tinim22 f/f b5 b2 tinis21 f/f tinim21 f/f b6 b3 tinis20 f/f tinim20 f/f b7 tinir6 tin23edge tin22edge tin21edge tin20edge data bus mjt input interrupt 3 irq11 (level) 4-source inputs
10 10-56 ver.0.10 d8 9 1011121314d15 tinis33 tinis32 tinis31 tinis30 tinim33 tinim32 tinim31 tinim30 d bit name function r w 8 tinis33 (tin33 interrupt status) 0 : no interrupt request 9 tinis32 (tin32 interrupt status) 1 : interrupt request generated 10 tinis31 (tin31 interrupt status) 11 tinis30 (tin30 interrupt status) 12 tinim33 (tin33 interrupt mask) 0 : enables interrupt request 13 tinim32 (tin32 interrupt mask) 1 : masks (disables) interrupt request 14 tinim31 (tin31 interrupt mask) 15 tinim30 (tin30 interrupt mask) w = : only writing a 0 is effective; when you write a 1, the previous value is retained. note : for tin24-tin29, there are no interrupt status and mask bits in mjt interrupt control registers because they do not have interrupt functions. n tin interrupt control register 7 (tinir7) figure 10.2.19 block diagram of tml1 input interrupt b8 tinis33 f/f tinim33 f/f b12 b9 tinis32 f/f tinim32 f/f b13 b10 tinis31 f/f tinim31 f/f b14 b11 tinis30 f/f tinim30 f/f b15 tinir7 tin33edge tin32edge tin31edge tin30edge data bus tml1 input interrupt irq18 (level) 4-source inputs
10 10-57 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tod07ima tod06ima tod05ima tod04ima tod03ima tod02ima tod01ima tod00ima d bit name function r w 0 tod07ima (tod0_7 interrupt mask) 0 : enables interrupt request 1 tod06ima (tod0_6 interrupt mask) 1 : masks (disables) interrupt request 2 tod05ima (tod0_5 interrupt mask) 3 tod04ima (tod0_4 interrupt mask) 4 tod03ima (tod0_3 interrupt mask) 5 tod02ima (tod0_2 interrupt mask) 6 tod01ima (tod0_1 interrupt mask) 7 tod00ima (tod0_0 interrupt mask) n tod0 interrupt status register (tod0ist) n tod0 interrupt mask register (tod0ima) d8 9 1011121314d15 tod07ist tod06ist tod05ist tod04ist tod03ist tod02ist tod01ist tod00ist d bit name function r w 8 tod07ist (tod0_7 interrupt status) 0 : no interrupt request 9 tod06ist (tod0_6 interrupt status) 1 : interrupt request generated 10 tod05ist (tod0_5 interrupt status) 11 tod04ist (tod0_4 interrupt status) 12 tod03ist (tod0_3 interrupt status) 13 tod02ist (tod0_2 interrupt status) 14 tod01ist (tod0_1 interrupt status) 15 tod00ist (tod0_0 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
10 10-58 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.20 block diagram of tod0 output interrupt b8 tod07ist f/f tod07ima f/f b0 b9 tod06ist f/f tod06ima f/f b1 b10 tod05ist f/f tod05ima f/f b2 b11 tod04ist f/f tod04ima f/f b3 b12 tod03ist f/f tod03ima f/f b4 tod0ima tod0ist tod07udf tod06udf tod05udf tod04udf tod03udf b13 tod02ist f/f tod02ima f/f b5 b14 tod01ist f/f tod01ima f/f b6 b15 tod00ist f/f tod00ima f/f b7 tod02udf tod01udf tod00udf data bus tod0 output interrupt 2 irq13 (level) 8-source inputs
10 10-59 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tod17ima tod16ima tod15ima tod14ima tod13ima tod12ima tod11ima tod10ima d bit name function r w 0 tod17ima (tod1_7 interrupt mask) 0 : enables interrupt request 1 tod16ima (tod1_6 interrupt mask) 1 : masks (disables) interrupt request 2 tod15ima (tod1_5 interrupt mask) 3 tod14ima (tod1_4 interrupt mask) 4 tod13ima (tod1_3 interrupt mask) 5 tod12ima (tod1_2 interrupt mask) 6 tod11ima (tod1_1 interrupt mask) 7 tod10ima (tod1_0 interrupt mask) n tod1 interrupt status register (tod1ist) n tod1 interrupt mask register (tod1ima) d8 9 1011121314d15 tod17ist tod16ist tod15ist tod14ist tod13ist tod12ist tod11ist tod10ist d bit name function r w 8 tod17ist (tod1_7 interrupt status) 0 : no interrupt request 9 tod16ist (tod1_6 interrupt status) 1 : interrupt request generated 10 tod15ist (tod1_5 interrupt status) 11 tod14ist (tod1_4 interrupt status) 12 tod13ist (tod1_3 interrupt status) 13 tod12ist (tod1_2 interrupt status) 14 tod11ist (tod1_1 interrupt status) 15 tod10ist (tod1_0 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
10 10-60 ver.0.10 multijunction timers 10.2 common units of multijunction timer d0123456d7 tom07ima tom06ima tom05ima tom04ima tom03ima tom02ima tom01ima tom00ima d bit name function r w 0 tom07ima (tom0_7 interrupt mask) 0 : enables interrupt request 1 tom06ima (tom0_6 interrupt mask) 1 : masks (disables) interrupt request 2 tom05ima (tom0_5 interrupt mask) 3 tom04ima (tom0_4 interrupt mask) 4 tom03ima (tom0_3 interrupt mask) 5 tom02ima (tom0_2 interrupt mask) 6 tom01ima (tom0_1 interrupt mask) 7 tom00ima (tom0_0 interrupt mask) n tom0 interrupt status register (tom0ist) n tom0 interrupt mask register (tom0ima) d8 9 1011121314d15 tom07ist tom06ist tom05ist tom04ist tom03ist tom02ist tom01ist tom00ist d bit name function r w 8 tom07ist (tom0_7 interrupt status) 0 : no interrupt request 9 tom06ist (tom0_6 interrupt status) 1 : interrupt request generated 10 tom05ist (tom0_5 interrupt status) 11 tom04ist (tom0_4 interrupt status) 12 tom03ist (tom0_3 interrupt status) 13 tom02ist (tom0_2 interrupt status) 14 tom01ist (tom0_1 interrupt status) 15 tom00ist (tom0_0 interrupt status) w = : only writing a 0 is effective; when you write a 1, the previous value is retained.
10 10-61 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.21 block diagram of tod1 + tom0 output interrupt (1/2) b8 tod17ist f/f tod17ima f/f b0 b9 tod16ist f/f tod16ima f/f b1 b10 tod15ist f/f tod15ima f/f b2 b11 tod14ist f/f tod14ima f/f b3 b12 tod13ist f/f tod13ima f/f b4 tod1ima tod1ist tod17udf tod16udf tod15udf tod14udf tod13udf b13 tod12ist f/f tod12ima f/f b5 b14 tod11ist f/f tod11ima f/f b6 b15 tod10ist f/f to 8 input sources in the next page f/f b7 tod12udf tod11udf tod10udf tod10ima data bus tod1 + tom0 output interrupt irq16 (level) 16-source inputs
10 10-62 ver.0.10 multijunction timers 10.2 common units of multijunction timer figure 10.2.22 block diagram of tod1 + tom0 output interrupt (2/2) b8 tom07ist f/f tom07ima f/f b0 b9 tom06ist f/f tom06ima f/f b1 b10 tom05ist f/f tom05ima f/f b2 b11 tom04ist f/f tom04ima f/f b3 b12 tom03ist f/f tom03ima f/f b4 tom0ima tom0ist tom07udf tom06udf tom05udf tom04udf tom03udf b13 tom02ist f/f tom02ima f/f b5 b14 tom01ist f/f tom01ima f/f b6 b15 tom00ist f/f f/f b7 tom02udf tom01udf tom00udf tom00ima to the preceding page data bus
10 10-63 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) 10.3 top (output-related 16-bit timer) 10.3.1 outline of top top (timer output) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: ? single-shot output mode ? delayed single-shot output mode ? continuous output mode the table below shows specifications of top. the diagram in the next page shows a block diagram of top. table 10.3.1 specifications of top (output-related 16-bit timer) item specification number of channels 11 channels counter 16-bit down-counter reload register 16-bit reload register correction register 16-bit correction register timer startup started by writing to enable bit in software or by enabling with external input (rising or falling edge or both) mode selection ? single-shot output mode ? delayed single-shot output mode ? continuous output mode interrupt generation can be generated by a counter underflow
10 10-64 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) figure 10.3.1 block diagram of top (output-related 16-bit timer) irq2 clk en udf top 0 clock bus input event bus clk en udf top 1 clk en udf top 2 clk en udf top 3 output event bus tclk0s to 0 irq9 3 2 1 0 clk en udf top 4 clk en udf top 5 tclk0 tin0 s s tin0s clk en udf top 6 clk en udf top 7 s s s irq9 tin1 irq9 tin2 s s clk en udf top 8 clk en udf top 9 clk en udf top 10 f/f0 f/f1 f/f2 f/f3 f/f4 f/f5 f/f6 f/f7 f/f8 f/f9 f/f10 s : selector f/f : output flip-flop s s s s s irq2 irq2 irq2 irq2 irq2 to 1 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 to 10 irq1 irq1 irq6 irq6 irq5 3 2 1 0 0 1 2 3 tin1s tin2s reload register down-counter correction register 3 2 1 0 3 2 1 0 0 1 2 3 (16 bits) drq7 drq8 drq9
10 10-65 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) 10.3.2 outline of each mode of top each mode of top is outlined below. for each top channel, only one of the following modes can be selected. (1) single-shot output mode in single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops without performing any operation. when after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), the content of the reload register is loaded into the counter synchronously with the count clock, letting the counter start counting. the counter counts down clock pulses and stops when it underflows after reaching the minimum count. the f/f output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. also, an interrupt can be generated when the counter underflows. (2) delayed single-shot output mode in delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. when after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. the first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. the f/f output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1) . also, an interrupt can be generated when the counter underflows first time and next. (3) continuous output mode in continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1).
10 10-66 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) when after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. this underflow causes the counter to be reloaded with the content of the reload register and start counting over again. thereafter, this operation is repeated each time an underflow occurs. to stop the counter, disable count by writing to the enable bit in software. the f/f output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. also, an interrupt can be generated each time the counter underflows.
10 10-67 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) 10.3.3 top related register map the diagram below shows a top-related register map. figure 10.3.2 top related register map (1/3) h'0080 0240 address d0 d7 +0 address +1 address d8 d15 h'0080 0242 h'0080 0244 h'0080 0246 h'0080 0250 h'0080 0252 h'0080 0254 h'0080 0256 h'0080 0260 h'0080 0262 h'0080 0264 h'0080 0266 h'0080 0270 h'0080 0272 h'0080 0274 h'0080 0276 top0 counter (top0ct) top0 reload register (top0rl) top0 correction register (top0cc) note: the registers enclosed in thick frames must always be accessed in halfwords. blank addresses are reserved. top1 counter (top1ct) top1 reload register (top1rl) top1 correction register (top1cc) top2 counter (top2ct) top2 reload register (top2rl) top2 correction register (top2cc) top3 counter (top3ct) top3 reload register (top3rl) top3 correction register (top3cc) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
10 10-68 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) figure 10.3.3 top related register map (2/3) h'0080 0280 d0 d7 d8 d15 h'0080 0282 h'0080 0284 h'0080 0286 h'0080 0290 h'0080 0292 h'0080 0294 h'0080 0296 h'0080 02a0 h'0080 02a2 h'0080 02a4 h'0080 02a6 h'0080 02b0 h'0080 02b2 h'0080 02b4 h'0080 02b6 h'0080 0298 h'0080 029a h'0080 029c top0-5 control register 0 (top05cr0) top0-5 control register 1 (top05cr1) h'0080 02aa h'0080 02a8 address +0 address +1 address top4 counter (top4ct) top4 reload register (top4rl) top4 correction register (top4cc) top5 counter (top5ct) top5 reload register (top5rl) top5 correction register (top5cc) top6,7 control register (top67cr) top6 counter (top6ct) top6 reload register (top6rl) top6 correction register (top6cc) top7 counter (top7ct) top7 reload register (top7rl) top7 correction register (top7cc) note: the registers enclosed in thick frames must always be accessed in halfwords. blank addresses are reserved. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
10 10-69 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) figure 10.3.4 top related register map (3/3) h'0080 02c0 d0 d7 d8 d15 h'0080 02c2 h'0080 02c4 h'0080 02c6 h'0080 02d0 h'0080 02d2 h'0080 02d4 h'0080 02d6 h'0080 02e0 h'0080 02e2 h'0080 02e4 h'0080 02e6 h'0080 02fa h'0080 02fc h'0080 02fe top0-10 external enable enable register (topeen) h'0080 02ea top8-10 control register (top810cr) h'0080 02e8 top0-10 enable protect register (toppro) top0-10 count enable register (topcen) address +0 address +1 address top8 counter (top8ct) top8 reload register (top8rl) top8 correction register (top8cc) note: the registers enclosed in thick frames must always be accessed in halfwords. blank addresses are reserved. top9 counter (top9ct) top9 reload register (top9rl) top9 correction register (top9cc) top9 counter (top9ct) top9 reload register (top9rl) top9 correction register (top9cc) top10 counter (top10ct) top10 reload register (top10rl) top10 correction register (top10cc) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
10 10-70 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) 10.3.4 top control registers the top control registers are used to select operation modes of top0-10 (single-shot, delayed single-shot, or continuous mode), as well as select the counter enable and counter clock sources. following four top control registers are provided for each timer group. ? top0-5 control register 0 (top05cr0) ? top0-5 control register 1 (top05cr1) ? top6, 7 control register (top67cr) ? top8-10 control register (top810cr)
10 10-71 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) n top0-5 control register 0 (top05cr0) note 1: this register must always be accessed in halfwords. note 2: always make sure the counter has stopped and is idle before setting or changing operation modes. d bit name function r w 0,1 top3m (top3 operation mode selection) 00: single-shot output mode 2,3 top2m (top2 operation mode selection) 01: delayed single-shot output mode 4,5 top1m (top1 operation mode selection) 1x: continuous output mode 6,7 top0m (top0 operation mode selection) 8 no functions assigned 0 C 9-10 top05ens 0xx: external tin0 input (top0-5 enable source selection) 100: input event bus 0 101: input event bus 1 110: input event bus 2 111: input event bus 3 12,13 no functions assigned 0 C 14,15 top05cks 00: clock bus 0 (top0-5 clock source selection) 01: clock bus 1 10: clock bus 2 11: clock bus 3 d01234567891011121314d15 top3m top2m top1m top0m top05ens top05cks
10 10-72 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) n top0-5 control register 1 (top05cr1) d8 9 1011121314d15 top5m top4m note: always make sure the counter has stopped and is idle before setting or changing operation modes. figure 10.3.5 outline diagram of top0-5 clock/enable inputs d bit name function r w 8-11 no functions assigned 0 C 12,13 top5m (top5 operation mode selection) 00: single-shot output mode 14,15 top4m (top4 operation mode selection) 01: delayed single-shot output mode 1x: continuous output mode clk en top 0 clock bus input event bus clk en top 1 clk en top 2 clk en top 3 3 2 1 0 clk en top 4 clk en top 5 s s : selector tin0 s tin0s 3 2 1 0 note: this diagram is shown for the explanation of top control registers, and is partly omitted.
10 10-73 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 top7m top6m top67ens top67cks top7 ens n top6,7 control register (top67cr) note 1: this register must always be accessed in halfwords. note 2: always make sure the counter has stopped and is idle before setting or changing operation modes. d bit name function r w 0 no functions assigned 0 C 1 top7ens 0: result selected by top67ens bit (top7 enable source selection) 1: top6 output 2,3 top7m (top7 operation mode selection) 00: single-shot output mode 01: delayed single-shot output mode 1x: continuous output mode 4,5 no functions assigned 0 C 6,7 top6m (top6 operation mode selection) 00: single-shot output mode 01: delayed single-shot output mode 1x: continuous output mode 8 no functions assigned 0 C 9-11 top67ens 0xx: external tin1 input (top6, top7 enable source selection) 100: input event bus 0 101: input event bus 1 110: input event bus 2 111: input event bus 3 12,13 no functions assigned 0 C 14,15 top67cks 00: clock bus 0 (top6, top7 clock source selection) 01: clock bus 1 10: clock bus 2 11: clock bus 3
10 10-74 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) figure 10.3.6 outline diagram of top6, top7 clock/enable inputs 3 2 1 0 clk en udf top 6 clk en udf top 7 s s tin1s tin1 s 3 2 1 0 s clock bus input event bus : selector note: this diagram is shown for the explanation of top control registers, and is partly omitted.
10 10-75 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) n top8-10 control register (top810cr) note 1: this register must always be accessed in halfwords. note 2: always make sure the counter has stopped and is idle before setting or changing operation modes. d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d15 top10m top9m top8m top810cks top 810 ens d bit name function r w 0,1 no functions assigned 0 C 2,3 top10m (top10 operation mode selection) 00: single-shot output mode 4,5 top9m (top9 operation mode selection) 01: delayed single-shot output mode 6,7 top8m (top8 operation mode selection) 1x: continuous output mode 8-10 no functions assigned 0 C 11 top810ens 0: external tin2 input (top8-10 enable source selection) 1: input event bus 3 12,13 no functions assigned 0 C 14,15 top810cks 00: clock bus 0 (top8-10 clock source selection) 01: clock bus 1 10: clock bus 2 01: clock bus 3
10 10-76 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) figure 10.3.7 outline diagram of top8-10 clock/enable inputs 3 2 1 0 tin2 tin2s s s clk en top 8 clk en top 9 clk en top 10 s 3 2 1 0 clock bus input event bus : selector note: this diagram is shown for the explanation of top control registers, and is partly omitted.
10 10-77 ver.0.10 multijunction timers 10.3 top (output-related 16-bit timer) 10.3.5 top counters (top0ct-top10ct) n top0 counter (top0ct) n top1 counter (top1ct) n top2 counter (top2ct) n top3 counter (top3ct) n top4 counter (top4ct) n top5 counter (top5ct) n top6 counter (top6ct) n top7 counter (top7ct) n top8 counter (top8ct) n top9 counter (top9ct) n top10 counter (top10ct)

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